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[1990] Proceedings of the International Conference on Application Specific Array Processors最新文献

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A database machine based on surrogate files 基于代理文件的数据库机器
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145443
S. M. Chung
{"title":"A database machine based on surrogate files","authors":"S. M. Chung","doi":"10.1109/ASAP.1990.145443","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145443","url":null,"abstract":"Concatenated code word (CCW) surrogate files are useful as indexes for very large knowledge bases to support logic programming inference mechanisms because of their small size and simple maintenance requirements. A parallel back-end database machine is proposed to speed up relation operations based on the CCW surrogate files. The basic idea of the machine is to reduce the amount of fact data to be transferred from the secondary storage systems to satisfy a query by performing relational operations on the CCW surrogate files first. The database machine consists of a number of surrogate file processors (SFPs) and extensional database processors (EDBPs) operating in SIMD mode. The performance of the system for parallel relational operations is evaluated for various cases.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116929995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Application-specific coprocessor computer architecture 专用的协处理器计算机体系结构
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145500
Y. Chu
{"title":"Application-specific coprocessor computer architecture","authors":"Y. Chu","doi":"10.1109/ASAP.1990.145500","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145500","url":null,"abstract":"The coprocessor computer architecture has a main processor and one or more coprocessors. The author proposes the use of the coprocessor computer architecture for realizing high-performance, application-specific parallel computers. The author presents a classification of coprocessor computer organization. Matching a coprocessor computer organization with a parallel algorithm is suggested. As an example, a lexical/parsing coprocessor, which can deliver tokens from lexical processing at the rate of one million per second and semantic-rule codes from parsing at the rate of 2.5 million per second is described. This coprocessor shortens compilation time, reduces compiler size, and lessens programmer effort. This result clearly shows the potential use of the coprocessor computer architecture for application-specific computers.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123620774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Systolic architecture for 2-D rank order filtering 二维秩序滤波的收缩结构
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145446
Jenq-Neng Hwang, J. Jong
{"title":"Systolic architecture for 2-D rank order filtering","authors":"Jenq-Neng Hwang, J. Jong","doi":"10.1109/ASAP.1990.145446","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145446","url":null,"abstract":"The proposed systolic design for 2-D rank order filtering has a wide variety of applications in image processing. It derives its architecture mainly from a systolic design for 1-D rank order filtering proposed previously. The adopted systolic design, called the sample oriented rank order filter design, takes advantage of the evaluated rank values in the current window for the evaluation of the rank values in the next window without explicitly sorting the data in the window. This makes it possible to convert a 2-D windowed data sequence into a 1-D windowed data sequence with multiple data sample exchange at each window movement, and the 1-D systolic design is thus applicable. By cascading many such 1-D systolic arrays into a 2-D array, and supplied with simple parallel-in-serial-out (PISO) logic, this architecture can achieve the maximally available parallelism with nearly 100% efficiency if either the pipeline interleaving or processor sharing technique is used. The design does not require the preloading of the whole 2-D data array, and line scanned images can be processed with negligible time delay.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116366844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An analog VLSI array processor for classical and connectionist AI 一个模拟VLSI阵列处理器的经典和连接的人工智能
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145473
J. W. Mills, Charles A. Daffinger
{"title":"An analog VLSI array processor for classical and connectionist AI","authors":"J. W. Mills, Charles A. Daffinger","doi":"10.1109/ASAP.1990.145473","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145473","url":null,"abstract":"The authors describe the architecture of an operational 31-cell CMOS VLSI Lukasiewicz logic array (LLA) which is regular, simple, area-efficient, and implemented with analog rather than digital processing elements. The prototype LLAs are programmed with input vectors derived from normal forms of sentences in the Lukasiewicz logic. This requires data inputs on the order of O(2/sup n/) for sentences in n implications, limits the size of the sentences that can be evaluated by a given LLA, and increases the number of pins needed on the VLSI package. The dual logic and algebraic semantics of Lukasiewicz logic allows LLAs to implement expert systems, neural networks and fuzzy logic functions. Schematic examples are given for each application, and results obtained by programming the prototype LLA as a fuzzy function generator show that the LLA implemented the notch function linearly, but with a slope that varied from that of the calculated function.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116183804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Building blocks for a new generation of application specific computing systems 新一代特定于应用程序的计算系统的构建模块
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145456
B. Baxter, G. Cox, T. Gross, H. T. Kung, D.O. O'Hallaron, C. Peterson, J. Webb, P. Wiley
{"title":"Building blocks for a new generation of application specific computing systems","authors":"B. Baxter, G. Cox, T. Gross, H. T. Kung, D.O. O'Hallaron, C. Peterson, J. Webb, P. Wiley","doi":"10.1109/ASAP.1990.145456","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145456","url":null,"abstract":"The iWarp processor, which integrates both communication and computation functions on a single VLSI component, is described. The iWarp component and subsystems including it are powerful building blocks for constructing a new generation of application-specific computing systems. These special-purpose systems can achieve very high performance, while maintaining a high degree of flexibility to address different needs of an application. In particular, iWarp systems deliver high computation bandwidth (up to 20 GFLOPS for a 1024 cell system), as well as high communication bandwidth (320 Mbytes/s per cell). Programming these systems is assisted by modern tools such as optimizing compilers and parallel program generators.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115424173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Linear arrays for residue mappers 残差映射器的线性阵列
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145468
Z. Sarkari, A. Skavantzos
{"title":"Linear arrays for residue mappers","authors":"Z. Sarkari, A. Skavantzos","doi":"10.1109/ASAP.1990.145468","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145468","url":null,"abstract":"Pipelined structures based on the residue number system (RNS) have been found suitable for high-speed arithmetic. The polynomial RNS (PRNS) can speed up digital signal processing (DSP)-related tasks like correlations and convolutions. The authors introduce pipelined arrays able to serve as mapping modules for PRNS-based functional units. Such mappings, involve polynomial evaluation coupled with modulo operations. The authors show how VLSI array processors can perform modulo operations in a parallel environment. A methodology is presented by which the reliability of such fast architectures can be ensured simply by probing into the mechanics of the computations involved. The proposed techniques provide a hardware base for PRNS implementations. At the same time, a reasonable degree of fault-tolerance can be guaranteed in the face of high system throughputs.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"30 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129485148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Programming environment for a line processor-SYMPATI-2 用于行处理器的编程环境- sympati -2
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145492
P. Fernandez, P. Adam, D. Juvin, J. Basille
{"title":"Programming environment for a line processor-SYMPATI-2","authors":"P. Fernandez, P. Adam, D. Juvin, J. Basille","doi":"10.1109/ASAP.1990.145492","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145492","url":null,"abstract":"The authors present the programming environment developed for the line processor SYMPATI-2. The main objective is to take advantage of the facilities provided by the parallel structure and make them easy to be used. The authors give the general characteristics of the SYMPATI-2 architecture and then present the programming environment and the 4 LP language. Some examples for illustrating the easy way one can use this structure are given. The authors show that 4 LP is relevant for pixel level processing. It makes it easy to program any algorithm operating at this level. The programs are flexible, taking advantage of parameterization possibilities. The results obtained provide a favorable quality factor. Common execution time for a 256*256 image within a 32 PE configuration is between some milliseconds and about 20 milliseconds for more complex operations.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126984341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A practical runtime test method for parallel lattice-gas automata 一种实用的并行格-气自动机运行测试方法
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145512
R. Squier, K. Steiglitz
{"title":"A practical runtime test method for parallel lattice-gas automata","authors":"R. Squier, K. Steiglitz","doi":"10.1109/ASAP.1990.145512","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145512","url":null,"abstract":"The authors describe a test method for lattice-gas automata of the type introduced by U. Frisch et al. (1986). The test method consists of inserting test patterns into the initial state of the automaton and using a graphics display to detect errors. The test patterns are carefully constructed limit cycles that are disrupted by errors occurring at any level of the simulator system. The patterns can be run independently to test the system for debugging purposes, or they can be run as sub-simulations embedded in a larger lattice-gas simulation to detect faults at runtime. The authors describe the use of this method on a prototype parallel machine for lattice-gas simulations, and discuss the range of systems that can make use of this type of test method. The test patterns detect all significant one-bit errors. Included are experimental results indicating that multiple bit errors are unlikely to escape detection.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131900019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault-tolerant array processors using N-and-half-track switches 使用n -半轨道开关的容错阵列处理器
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145478
Jack S. N. Jean
{"title":"Fault-tolerant array processors using N-and-half-track switches","authors":"Jack S. N. Jean","doi":"10.1109/ASAP.1990.145478","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145478","url":null,"abstract":"The author addresses the fault tolerance issue for rectangular arrays of a large number of processors. An array grid model based on n1/2-track switches is adopted. This model is a generalization of previous models using 1 1/2-track switches and 2 1/2-track switches. A reconfigurability theorem for n1/2 track arrays is established and a concept of pseudo processing elements (PEs) is introduced to decompose a routing problem into problems with smaller track numbers. Therefore, with the decomposition technique, only the routing algorithm developed for 1 1/2-track arrays is required. Simulation results for the 1 1/2-track array and 2 1/2-track array are given.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134521823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of systolic algorithms using pipelined functional units 使用流水线功能单元实现收缩算法
[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI: 10.1109/ASAP.1990.145464
M. Valero-García, J. Navarro, J. Llabería, M. Valero
{"title":"Implementation of systolic algorithms using pipelined functional units","authors":"M. Valero-García, J. Navarro, J. Llabería, M. Valero","doi":"10.1109/ASAP.1990.145464","DOIUrl":"https://doi.org/10.1109/ASAP.1990.145464","url":null,"abstract":"The authors present a method to implement systolic algorithms (SAs) using pipelined functional units (PFUs). This kind of unit makes it possible to improve the throughput of a processor because of the possibility of initiating a new operation before the previous one has been completed. The method permits transformation of a SA so that it can be efficiently executed using PFUs. The method is based on two temporal transformations (slowdown and retiming) and one spatial transformation (coalescing). The temporal transformations permit the modification of the SA in such a way that dependences established by the PFU are preserved. The spatial transformation improves the hardware utilization. The method was applied to 1-D SAs with data contraflow. To demonstrate the effectiveness of the method, the authors describe an efficient implementation of a non-time-homogeneous SA with data contraflow for QR decomposition.<<ETX>>","PeriodicalId":438078,"journal":{"name":"[1990] Proceedings of the International Conference on Application Specific Array Processors","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132698697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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