专用的协处理器计算机体系结构

[1990] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1990-09-05 DOI:10.1109/ASAP.1990.145500

Y. Chu

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引用次数: 2

摘要

协处理器计算机体系结构有一个主处理器和一个或多个协处理器。作者建议使用协处理器计算机体系结构来实现高性能、特定应用的并行计算机。提出了协处理器计算机组织的分类。提出了一种用并行算法匹配协处理器计算机组织的方法。作为一个示例，描述了一个词法/解析协处理器，它可以以每秒一百万的速度从词法处理中传递令牌，并以每秒250万的速度从解析中传递语义规则代码。这种协处理器缩短了编译时间，减小了编译器的大小，并减少了程序员的工作量。这一结果清楚地显示了协处理器计算机体系结构在特定应用计算机上的潜在用途。

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Application-specific coprocessor computer architecture

The coprocessor computer architecture has a main processor and one or more coprocessors. The author proposes the use of the coprocessor computer architecture for realizing high-performance, application-specific parallel computers. The author presents a classification of coprocessor computer organization. Matching a coprocessor computer organization with a parallel algorithm is suggested. As an example, a lexical/parsing coprocessor, which can deliver tokens from lexical processing at the rate of one million per second and semantic-rule codes from parsing at the rate of 2.5 million per second is described. This coprocessor shortens compilation time, reduces compiler size, and lessens programmer effort. This result clearly shows the potential use of the coprocessor computer architecture for application-specific computers.<>

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[1990] Proceedings of the International Conference on Application Specific Array Processors

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