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FPGA based fast complex wavelet packet modulation(FCWPM) system 基于FPGA的快速复杂小波包调制系统
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671610
H. Abdullah, Fadhil S. Hassan, A. Valenzuela
{"title":"FPGA based fast complex wavelet packet modulation(FCWPM) system","authors":"H. Abdullah, Fadhil S. Hassan, A. Valenzuela","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671610","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671610","url":null,"abstract":"This paper presents an efficient design and implementation of a complex wavelet packet modulation (CWPM) multicarrier communication transceiver using an FPGA platform. A fast algorithm already proposed for high data rate WPM systems has been applied to CWPM systems for speed enhancement. The theoretical performance of the computation algorithm is analyzed. The design uses 16-point Fast Wavelet Packet Transform/Inverse Wavelet Packet Transform (FWPT/IFWPT) of the Haar family as the core processing module. All the proposed fast CWPM (FCWPM) system modules are designed and implemented using VHDL programming language. Software tools used in this work include Altera Quartus II 9.1 and ModelSim Altera 6.5b. A Cyclone III board is used for the implementation. The hardware simulation results show that the use of fast Haar wavelet packet transform algorithms to implement complex wavelet packet modulation systems significantly increases its speed as compared with direct implementations.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115928892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimized rate matching architecture for a LTE-Advanced FPGA-based PHY 基于LTE-Advanced fpga的物理层的优化速率匹配体系结构
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671636
K. Lenzi, Jose A. Bianco F, F. A. D. de Figueiredo, F. Figueiredo
{"title":"Optimized rate matching architecture for a LTE-Advanced FPGA-based PHY","authors":"K. Lenzi, Jose A. Bianco F, F. A. D. de Figueiredo, F. Figueiredo","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671636","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671636","url":null,"abstract":"In this paper we present an optimized rate matching architecture for a LTE-Advanced FPGA-based physical layer. Since LTE-Advanced can reach up to rates of 1 Gbps in downlink, and since rate matching is in that critical path, it is very important that the design of the hardware architecture be efficient enough to allow this high data rate with little resources as possible. If not well planned, implementations on FPGAs can be quite challenging, limiting the choices of speed grades and FPGAs sizes capable of supporting such requirements. We propose efficient hardware architecture for the LTE-Advanced rate matching generic procedure; occupying only 218 slices and 9 block RAMs and performing in frequencies greater than 400 MHz in a FPGA-based solution.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122614153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design optimization for diminution of 5.75 GHZ Chebyshev bandpass filter 减小5.75 GHZ切比雪夫带通滤波器的设计优化
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671602
Shankar Duraikannan, Mahir Salum Awadh
{"title":"Design optimization for diminution of 5.75 GHZ Chebyshev bandpass filter","authors":"Shankar Duraikannan, Mahir Salum Awadh","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671602","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671602","url":null,"abstract":"This paper presents the design and evaluation of 5.75 GHz Chebyshev bandpass filter for WLAN Applications. The proposed design is aimed at the diminution of filter structures. 9th order Chebyshev filter structures are designed using Rogger Duroid (TLY-5A) and FR4. The performances of designed filter structures are evaluated in comparison with the conventional filter structure. Results shows that the size of the designed Chebyshev 9th order band pass filter has been reduced by 60.4% in term of area in comparison with the conventional filter. Also the filters designed using TLY-5A exhibit a superior performance in comparison with the filters designed using FR4.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116885526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET 基于sub- 32nm双栅极mosfet的低功耗高速比较器设计
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671626
V. Bhumireddy, K. Shaik, A. Amara, S. Sen, C. Parikh, D. Nagchoudhuri, A. Ioinovici
{"title":"Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET","authors":"V. Bhumireddy, K. Shaik, A. Amara, S. Sen, C. Parikh, D. Nagchoudhuri, A. Ioinovici","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671626","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671626","url":null,"abstract":"A novel latch-based comparator is proposed for Successive Approximation (SA) Analog to Digital Convertor(ADC) with sub-32nm Double Gate MOSFETs(DG-MOSFET). The regeneration time of the latch is improved by using an extra positive feedback which uses the threshold voltage modulation property of DG-MOSFET. Simulation of the proposed comparator with CEA-LETI's DG-MOSFETmodels resulted in a delay of 25ps. The average power dissipation over one clock period is ≤ 1μW up to the clock frequency of 100MHz, which increases as frequency is increased resulting in an average power of 6.54μW at 1GHz, for an input voltage differential of 50mV.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126837702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design and simulation of low voltage RF MEMS series switch array 低压射频MEMS系列开关阵列的设计与仿真
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671639
K. S. Beh, H. Jaafar, Nurul Amziah Md Yunus, S. Shafie
{"title":"Design and simulation of low voltage RF MEMS series switch array","authors":"K. S. Beh, H. Jaafar, Nurul Amziah Md Yunus, S. Shafie","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671639","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671639","url":null,"abstract":"In radio frequency (RF) applications, micro-electromechanical system (MEMS) offers better isolation, low loss, and low power consumption over the electronic switches. The satellite system and telecommunication system require high performance of switching array. In this project, a switching array size of 2×2 is modeled using 6 units of identical MEMS series switch. The switch array is able to perform connection through 2 input ports and 2 output ports. The simulation is performed using CoventorWare, and the electromagnetic characteristics are simulated using EM3DS. A single series switch has pulled in voltage of 4.5V, isolation of -25.3 dB, and insertion loss of -0.038 dB at 12 GHz. For the overall performances of 2×2 arrays, the simulation shows insertion loss less than -0.1 dB, and isolation better than -40 dB at 12GHz.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126113088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
ZnO doping profile effect on CIGS solar cells efficiency and parasitic resistive losses based on cells equivalent circuit 基于等效电路的ZnO掺杂轮廓对CIGS太阳能电池效率和寄生电阻损耗的影响
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671641
Nima Khoshsirat, Nurul Amziah Md Yunus, M. Hamidon, S. Shafie, N. Amin
{"title":"ZnO doping profile effect on CIGS solar cells efficiency and parasitic resistive losses based on cells equivalent circuit","authors":"Nima Khoshsirat, Nurul Amziah Md Yunus, M. Hamidon, S. Shafie, N. Amin","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671641","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671641","url":null,"abstract":"The window layer of the CIGS thin film solar cells plays the role of transparent front contact and the n-side of pn-heterojunction. Thus the variation of window layers electrical and optical properties can affect the cell performance. Properties of Al-doped Zinc oxide (ZnO) thin film as most common used window layer for CIGS solar cells were studied via simulation using the simulation program called SCAPS-1D. This study is aimed to find the effect of ZnO layer doping profile on cell performance. It is found that increasing Al-content up to 5% in ZnO layer will lead to increasing the cell efficiency and will decrease the cell series and shunt resistance.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123352101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A color space study for skin lesion segmentation 皮肤病灶分割的色彩空间研究
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671629
H. Nisar, Y. Ch'ng, Tsyr Yee Chew, V. Yap, K. Yeap, J. Tang
{"title":"A color space study for skin lesion segmentation","authors":"H. Nisar, Y. Ch'ng, Tsyr Yee Chew, V. Yap, K. Yeap, J. Tang","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671629","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671629","url":null,"abstract":"The objective of this research is to identify the most suitable color model for segmentation of Eczema skin lesions. Eczema is a type of Atopic Dermatitis that is diagnosed by the dermatologists by visual inspection hence by subjective assessment. For segmentation, K-means clustering has been used. Four color spaces, i.e. HSI, CMY, YCbCr and CIELAB are used for comparisons. The final conclusion is made on the basis of the results for sensitivity, specificity and accuracy for each technique. It has been observed that the color channel “H” of HSI; followed by “a” of CIELab; gives better segmentation results.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122865857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A self testable hardware for memory 一个可自我测试的内存硬件
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671631
M. Saha, B. Sikdar
{"title":"A self testable hardware for memory","authors":"M. Saha, B. Sikdar","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671631","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671631","url":null,"abstract":"This work develops a self testable hardware for memory to achieve high speed testing. The BIST (built-in-self-test) architecture, realizing the efficient March algorithm, employs the special class of single length cycle attractor cellular automata (CA) defined in 5-neighborhood. The design ensures decision on the fault in memory even if the BIST logic is faulty. This overcomes the inability of the classical test hardware designed with the ex - or and or logic. The proposed test hardware exhibits better efficiency in comparison to the state-of-the-art memory test designs. The modular structure of CA, employed for the BIST design, incurs hardware overhead that is insignificant compared to the cost of a memory of large size. The design also reduces the test time while avoiding the bit by bit comparison of memory words, required in the conventional test designs.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132398288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The characteristic analysis of CPW bandpass filter by magnetic material 磁性材料CPW带通滤波器的特性分析
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671627
Wu-Shiung Feng, Prasenjit Chatterjee, Hsiu-Chuan Lin, C. Yeh, Ho-hsin Li
{"title":"The characteristic analysis of CPW bandpass filter by magnetic material","authors":"Wu-Shiung Feng, Prasenjit Chatterjee, Hsiu-Chuan Lin, C. Yeh, Ho-hsin Li","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671627","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671627","url":null,"abstract":"This paper presents the characteristic analysis of coplanar waveguide (CPW) filters with flaky magnetic material on top of the filter. This 2-port CPW 2.3-GHz filter with single-ended input single-ended (SISO) output is fabricated on FR4 (Flame Retardant 4) substrate, to discuss the influence of magnetic material on the variations of operating frequency, bandwidth and center frequency. According to measurement results, when magnetic material with different thicknesses is placed on the CPW filter, the center frequency of the filter decreases as the thickness of the magnetic material increases, and vice versa. The frequency decreases by 20% as the thickness of 4mm magnetic material on the top. The lower and upper sides of passband frequency are reduced by 3.29MHz and 6.71MHz per mm thickness of magnetic material on average, respectively. This change can be achieved due to the magnetic materials' layers on top of CPW filter not by changing the actual hardware of the circuit.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122090720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Round Robin Arbiters on router's performance for NoCs on FPGAs 轮询仲裁者对fpga上noc路由器性能的影响
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671635
Maher Abdelrasoul, M. Ragab, V. Goulart
{"title":"Impact of Round Robin Arbiters on router's performance for NoCs on FPGAs","authors":"Maher Abdelrasoul, M. Ragab, V. Goulart","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671635","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671635","url":null,"abstract":"Routers are the basic building blocks of NoCs and their throughput critically affects the whole network performance. One of the most important building blocks in the router is the arbitration circuit, which controls granting to various requesters when the network is heavily used. In this work we focus on RRAs (Round Robin Arbiters) and their impact on router's performance and area on various FPGAs. We also propose a new arbiter design, Truth-Table arbiter, specifically aimed towards FPGA devices. Our results show that the arbiter circuit influences the router performance in most cases. Moreover, our newly proposed Truth-Table arbiter shows the same performance as the best existing arbiters but with smaller total area overhead and ease of design.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130974980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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