发布求助
文献互助 智能选刊 最新文献

2013 IEEE International Conference on Circuits and Systems (ICCAS)最新文献

筛选
英文 中文
Design of a 4-bit ripple adder using Quantum-dot Cellular Automata (QCA) 基于量子点元胞自动机的4位纹波加法器设计
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671634
Sarah Tji Yan Chan, C. F. Chau, Azrul bin Ghazali
{"title":"Design of a 4-bit ripple adder using Quantum-dot Cellular Automata (QCA)","authors":"Sarah Tji Yan Chan, C. F. Chau, Azrul bin Ghazali","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671634","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671634","url":null,"abstract":"Quantum-dot Cellular Automata (QCA) is one of the new emerging nanotechnologies explored as an alternative to current CMOS designs. This paper presents the fundamental concepts of QCA and QCA-based logic design. Basic QCA logic circuits such as the inverter, three-input majority gate and five-input majority gate are studied and implemented using QCADesigner. To demonstrate the practical use of using QCA in logic design, a 4-bit ripple adder using a combined concepts from the conventional RCA and CLA is proposed using 20 three-input majority gates, 4 five-input majority gates and 12 inverters. The proposed adder uses 1246 cells which resulted in an area of 1.75um × 1.43um, and a latency of 5.75 clock cycles.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124393750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Phase-compensation-circuit design using iterative linear-programming scheme 基于迭代线性规划的相位补偿电路设计
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671590
N. Ito, Tianliang Deng
{"title":"Phase-compensation-circuit design using iterative linear-programming scheme","authors":"N. Ito, Tianliang Deng","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671590","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671590","url":null,"abstract":"This paper proposes a new method for designing recursive all-pass (AP) phase-compensation-network that is useful in equalizing non-linear phase communication channels. For a given phase specification, we first derive a new phase-error that is an explicit non-linear function of the phase-compensation-network coefficients, and then propose an iterative scheme for minimizing the maximum phase-error such that the maximum phase-error can be minimized by utilizing a linear-programming (LP) technique. Such a design is called minimax design. Therefore, the resulting AP phase-compensation-network minimizes the worst-case phase-error and the iterative LP scheme obtains the optimal coefficients. As compared to the existing LP design and second-order-cone-programming (SOCP) design, the iterative LP scheme can achieve much more accurate minimax design. An example is given to show the improved performance of the iterative LP design over the existing LP and SOCP designs.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116224318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A fixed frequency continuous conduction LCCL series resonant inverter fed high voltage DC-DC converter 一种定频连续导通LCCL串联谐振逆变器馈入高压DC-DC变换器
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671608
A. Amir, S. Taib, S. Iqbal
{"title":"A fixed frequency continuous conduction LCCL series resonant inverter fed high voltage DC-DC converter","authors":"A. Amir, S. Taib, S. Iqbal","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671608","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671608","url":null,"abstract":"This paper presents a continuous conduction mode LCCL series resonant inverter fed high voltage dc-dc converter. The proposed converter is derived by adding an inductor in parallel with a capacitor and another capacitor in series with the leakage inductance of the transformer forming a resonant tank. The proposed converter is capable to reduce the parasitic oscillations where all of the parasitic capacitance and leakage inductances are absorbed by the resonant tank circuit. The proposed topology was simulated using PSPICE software. The obtained results show that proposed converter provide a wide range of output voltage control, low output voltage ripple over the entire range and low current stress at light load compare to the conventional circuit.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130127970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Voltage-mode PID controller using DDCCs and all-grounded passive components 电压型PID控制器采用ddcc和全接地无源元件
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671622
M. Kumngern
{"title":"Voltage-mode PID controller using DDCCs and all-grounded passive components","authors":"M. Kumngern","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671622","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671622","url":null,"abstract":"This paper presents a new voltage-mode proportional-integral-derivative (PID) controller using the differential difference current conveyors as active elements. The proposed PID controller uses all-grounded passive components which is highly suitable for integrated circuit implementation. The proportional gain, the integral time constant and the derivative time constant parameters can be independently controlled. For controlling the PID controller parameters, the circuit dose not need passive component-matching condition. The PSPICE simulation results are used to confirm the characteristics of the proposed PID controller.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126887765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Dual-frequency impedance transformer with a transmission zero 具有传输零的双频阻抗变压器
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671616
Ming-Lin Chuang, Ming-Tien Wu
{"title":"Dual-frequency impedance transformer with a transmission zero","authors":"Ming-Lin Chuang, Ming-Tien Wu","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671616","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671616","url":null,"abstract":"This work presents a shunt-stub dual-frequency transformer with a controllable transmission zero. The transformer is used to connect two circuit modules. The output circuit module has different input complex impedances at two uncorrelated frequencies. The proposed transformer not only provides a good match between the two circuit modules, but also generates an additional transmission zero such that some unwanted signal can be suppressed. The proposed impedance transformer has two configurations. Both configurations consist of cascaded transmission lines and shunt open stub that is the cause of the additional transmission zero. The numerical simulation shows a good performance satisfying the desired specifications.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130525252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Gain stabilization mechanism through dynamic common mode feedback and gain booster in Folded Cascode Track and Hold (THA) circuit 折叠级联跟踪保持(THA)电路中通过动态共模反馈和增益增强实现增益稳定机制
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671569
M. A. Abas, A. Asyraf
{"title":"Gain stabilization mechanism through dynamic common mode feedback and gain booster in Folded Cascode Track and Hold (THA) circuit","authors":"M. A. Abas, A. Asyraf","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671569","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671569","url":null,"abstract":"A low power Folded Cascode Track and Hold Amplifier (THA) circuit has been designed and analysed. The design of THA is to facilitate the development of ADC with specification 12-bit resolution, 125kSPS, and 1MHz. THA is used to sample and hold the input signal before it is being digitized. Ideally, signal that passed through THA circuit should not degrade the quality. Therefore high gain factor is very important to maintain the virtual ground on THA circuit. A simulation analysis was carried out to explore the operation of three different types of Folded Cascode circuits with the aims to identify the best techniques for increasing gain, decreasing speed and good ICMR parameter. The simulation was carried out at gate level using CMOS 0.18μm mixed signal process technology.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129044816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and implementation of CMOS low-noise amplifier for 40-GHz radio-over-fiber (RoF) system 40ghz光纤无线电(RoF)系统CMOS低噪声放大器的设计与实现
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671615
Maisurah M. H. Siti, E. F. Nazif, S. A. Enche Ab Rahim, A. Marzuki, A. Nigam
{"title":"Design and implementation of CMOS low-noise amplifier for 40-GHz radio-over-fiber (RoF) system","authors":"Maisurah M. H. Siti, E. F. Nazif, S. A. Enche Ab Rahim, A. Marzuki, A. Nigam","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671615","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671615","url":null,"abstract":"This paper presents the design of low-noise amplifier (LNA) implemented using 0.13-μm CMOS technology. The LNA was design to support the implementation of a remote antenna unit (RAU) constructed for a 40-GHz radio-over-fiber (RoF) system. The LNA designed for the RAU transmitter achieve a small-signal gain of 14.72-dB with a noise figure of 5.56-dB at 41-GHz. The LNA designed for the RAU receiver achieve a small-signal gain of 13.38-dB with a noise figure of 5.94-dB at 38.5-GHz. Both LNAs consumed 34.7-mW power from a 1.2-V supply voltage.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126763530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An efficient signal acquisition with an adaptive rate A/D conversion 一个有效的信号采集与自适应速率的A/D转换
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671611
S. Qaisar, R. Yahiaoui, T. Gharbi
{"title":"An efficient signal acquisition with an adaptive rate A/D conversion","authors":"S. Qaisar, R. Yahiaoui, T. Gharbi","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671611","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671611","url":null,"abstract":"The analog to digital conversion is an elementary part of the modern electronic systems. Almost all existing ADCs (Analog to Digital Converters) are based on the uniform sampling theory. It makes the signal acquisition time-invariant. Therefore, it can render a useless increase of the system activity, especially in the case of sporadic signals. Thus, an adaptive rate ADC which is based on the cross-level sampling is devised. It can adapt its conversion activity according to the input signal local variations. Therefore, it provides an intelligent signal acquisition which leads towards an efficient solution. The proposed ADC performance is studied for a speech acquisition. Results show a drastic reduction in the acquired number of samples and therefore promise a significant enhancement in the system power efficiency compared to the classical approach. A method to measure the proposed converter resolution is described. Moreover, its design flow is also presented.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126066577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A new lightweight and high performance AES S-box using modular design 采用模块化设计的新型轻量级高性能AES S-box
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671613
Wong Ming Ming, Dennis Wong Mou Ling
{"title":"A new lightweight and high performance AES S-box using modular design","authors":"Wong Ming Ming, Dennis Wong Mou Ling","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671613","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671613","url":null,"abstract":"Composite field arithmetic (CFA) is often utilized to create compact AES S-box implementation. However, the resultant circuitry is complex with long critical path and it induces high dynamic power consumption. In this paper, we presented a new architectural optimization in CFA which enhances the speed performance of the compact AES S-box and reduces its dynamic power consumption at the same time. The proposed methodology transforms and partitions the three-level CFA isomorphism in AES S-box into modules of logic equations, consisting of AND and XOR gates. This approach produces a highly modular design that makes effective pipelining possible. In this study, we also presented a new GF(24) multiplier for lightweight AES applications. For validation, the new AES S-box was implemented on Cyclone III EP2C5T144C6. It has a total of 66 logic elements (LEs), 36 registers and having maximum operating frequency of 346 MHz and a total dynamic power consumption of 1.84 mW.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"30 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120883879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Biomedical 3xVDD current micro-stimulator using standard 0.35um CMOS process 生物医学3xVDD电流微刺激器采用标准0.35um CMOS工艺
2013 IEEE International Conference on Circuits and Systems (ICCAS) Pub Date : 2013-11-21 DOI: 10.1109/CIRCUITSANDSYSTEMS.2013.6671638
Tzung-Je Lee, Hsin-Chang Chen
{"title":"Biomedical 3xVDD current micro-stimulator using standard 0.35um CMOS process","authors":"Tzung-Je Lee, Hsin-Chang Chen","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671638","DOIUrl":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671638","url":null,"abstract":"This paper proposes a 3xVDD current micro-stimulator using the 3.3 V devices in standard 0.35 μm CMOS process for the implantable biomedical application. Traditional implantable biomedical micro-stimulators suffer from the reliability and saturation problem when the high impedance electrode and tissue are driven. By using the HV (high-voltage) protection circuit, the proposed design can avoid the gate-oxide overstress and reliability problem due to the 3xVDD voltage supply. The proposed design is applied to the 3xVDD power supply voltage and provides a maximum stimulating current of 108 uA with the output voltage swing of 7.56 V for the high-impedance load of 70 kΩ. The maximum stimulating current frequency is simulated to be 100 kHz.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128400082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信