{"title":"基于量子点元胞自动机的4位纹波加法器设计","authors":"Sarah Tji Yan Chan, C. F. Chau, Azrul bin Ghazali","doi":"10.1109/CIRCUITSANDSYSTEMS.2013.6671634","DOIUrl":null,"url":null,"abstract":"Quantum-dot Cellular Automata (QCA) is one of the new emerging nanotechnologies explored as an alternative to current CMOS designs. This paper presents the fundamental concepts of QCA and QCA-based logic design. Basic QCA logic circuits such as the inverter, three-input majority gate and five-input majority gate are studied and implemented using QCADesigner. To demonstrate the practical use of using QCA in logic design, a 4-bit ripple adder using a combined concepts from the conventional RCA and CLA is proposed using 20 three-input majority gates, 4 five-input majority gates and 12 inverters. The proposed adder uses 1246 cells which resulted in an area of 1.75um × 1.43um, and a latency of 5.75 clock cycles.","PeriodicalId":436232,"journal":{"name":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"Design of a 4-bit ripple adder using Quantum-dot Cellular Automata (QCA)\",\"authors\":\"Sarah Tji Yan Chan, C. F. Chau, Azrul bin Ghazali\",\"doi\":\"10.1109/CIRCUITSANDSYSTEMS.2013.6671634\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Quantum-dot Cellular Automata (QCA) is one of the new emerging nanotechnologies explored as an alternative to current CMOS designs. This paper presents the fundamental concepts of QCA and QCA-based logic design. Basic QCA logic circuits such as the inverter, three-input majority gate and five-input majority gate are studied and implemented using QCADesigner. To demonstrate the practical use of using QCA in logic design, a 4-bit ripple adder using a combined concepts from the conventional RCA and CLA is proposed using 20 three-input majority gates, 4 five-input majority gates and 12 inverters. The proposed adder uses 1246 cells which resulted in an area of 1.75um × 1.43um, and a latency of 5.75 clock cycles.\",\"PeriodicalId\":436232,\"journal\":{\"name\":\"2013 IEEE International Conference on Circuits and Systems (ICCAS)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Conference on Circuits and Systems (ICCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671634\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference on Circuits and Systems (ICCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CIRCUITSANDSYSTEMS.2013.6671634","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a 4-bit ripple adder using Quantum-dot Cellular Automata (QCA)
Quantum-dot Cellular Automata (QCA) is one of the new emerging nanotechnologies explored as an alternative to current CMOS designs. This paper presents the fundamental concepts of QCA and QCA-based logic design. Basic QCA logic circuits such as the inverter, three-input majority gate and five-input majority gate are studied and implemented using QCADesigner. To demonstrate the practical use of using QCA in logic design, a 4-bit ripple adder using a combined concepts from the conventional RCA and CLA is proposed using 20 three-input majority gates, 4 five-input majority gates and 12 inverters. The proposed adder uses 1246 cells which resulted in an area of 1.75um × 1.43um, and a latency of 5.75 clock cycles.