A self testable hardware for memory

This work develops a self testable hardware for memory to achieve high speed testing. The BIST (built-in-self-test) architecture, realizing the efficient March algorithm, employs the special class of single length cycle attractor cellular automata (CA) defined in 5-neighborhood. The design ensures decision on the fault in memory even if the BIST logic is faulty. This overcomes the inability of the classical test hardware designed with the ex - or and or logic. The proposed test hardware exhibits better efficiency in comparison to the state-of-the-art memory test designs. The modular structure of CA, employed for the BIST design, incurs hardware overhead that is insignificant compared to the cost of a memory of large size. The design also reduces the test time while avoiding the bit by bit comparison of memory words, required in the conventional test designs.