发布求助
文献互助 智能选刊 最新文献

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献

筛选
英文 中文
The first EDA MOOC: Teaching design automation to planet earth 第一个EDA MOOC:将设计自动化教授给地球
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593230
Rob A. Rutenbar
{"title":"The first EDA MOOC: Teaching design automation to planet earth","authors":"Rob A. Rutenbar","doi":"10.1145/2593069.2593230","DOIUrl":"https://doi.org/10.1145/2593069.2593230","url":null,"abstract":"Massive Open Online Courses (MOOCs) can deliver advanced course material at planetary scale, combining internet-based video content delivery, and cloud-based assignments. From March to May 2013, I taught the world's first EDA MOOC, entitled VLSI CAD: Logic to Layout, based on roughly 20 years of experience teaching electronic design automation in a conventional face-to-face classroom setting. Over 17,000 participants registered for this MOOC. This paper summarizes my experience with teaching EDA at planetary scale: how we covered ASIC synthesis, verification, layout, and timing; how we built cloud resources to enable students to experiment with open-source tools; how we designed software projects and deployed cloud-based auto-graders to support realistic EDA tool projects. The paper also discusses what MOOCs could mean to the dynamism of the EDA community.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130699243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Automatic verification of Floating Point Units 浮点单位的自动验证
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593096
Udo Krautz, Viresh Paruthi, Anand Arunagiri, Sujeet Kumar, Shweta Pujar, Tina Babinsky
{"title":"Automatic verification of Floating Point Units","authors":"Udo Krautz, Viresh Paruthi, Anand Arunagiri, Sujeet Kumar, Shweta Pujar, Tina Babinsky","doi":"10.1145/2593069.2593096","DOIUrl":"https://doi.org/10.1145/2593069.2593096","url":null,"abstract":"Floating Point Units (FPUs) pose a singular challenge for traditional verification methods, such as coverage driven simulation, given the large and complex data paths and intricate control structures which renders those methods incomplete and error prone. Formal verification (FV) has been successfully leveraged to achieve the high level of quality desired of these critical logics. Typically, FV-based approaches to verify FPUs rely on introducing higher level abstractions to allow reasoning. This however has to be done manually, and quickly becomes tedious for optimized bit level implementations on board high performance microprocessors. Automated formal methods working directly on the bit level and providing a full end-to-end check exist but are limited to single instructions (issued in an empty pipeline), hence lack in checking control aspects related to inter-instruction interactions, or pipeline control. In this paper we present an approach based on equivalence checking to overcome the single instruction limitation for automated bit level proofs in the formal verification of FPUs. The sequential execution of instructions is modeled by two instances of the design-under-test. One of the instances acts as a reference model for the other. This allows for large numbers of internal equivalences to be leveraged by equivalence checking techniques. We show that this method is capable of proving instruction sequences for industrial FPU designs. Together with a proof of correctness of individual instructions it guarantees correctness of the FPU design as a whole. In our experience this is a one of a kind approach to perform automated end-to-end verification of FPUs.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128563182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Data mining in EDA - Basic principles, promises, and constraints EDA中的数据挖掘——基本原则、承诺和约束
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2596675
Li-C. Wang, M. Abadir
{"title":"Data mining in EDA - Basic principles, promises, and constraints","authors":"Li-C. Wang, M. Abadir","doi":"10.1145/2593069.2596675","DOIUrl":"https://doi.org/10.1145/2593069.2596675","url":null,"abstract":"This paper discusses the basic principles of applying data mining in Electronic Design Automation. It begins by introducing several important concepts in statistical learning and summarizes different types of learning algorithms. Then, the experience of developing a practical data mining application is described, including promises that are demonstrated through positive results based on industrial settings and constraints explained in their respective application contexts.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133243623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Demand-driven mixture preparation and droplet streaming using digital microfluidic biochips 数字微流控生物芯片的需求驱动混合液制备和液滴流
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593119
Sudip Roy, Srijan Kumar, P. Chakrabarti, B. Bhattacharya, K. Chakrabarty
{"title":"Demand-driven mixture preparation and droplet streaming using digital microfluidic biochips","authors":"Sudip Roy, Srijan Kumar, P. Chakrabarti, B. Bhattacharya, K. Chakrabarty","doi":"10.1145/2593069.2593119","DOIUrl":"https://doi.org/10.1145/2593069.2593119","url":null,"abstract":"In many biochemical protocols, such as polymerase chain reaction, a mixture of fluids in a certain ratio is repeatedly required, and hence a sufficient quantity of the mixture must be supplied for assay completion. Existing sample-preparation algorithms based on digital microfluidics (DMF) emit two target droplets in one pass, and costly multiple passes are required to sustain the emission of the mixture droplet. To alleviate this problem, we design a streaming engine on a DMF biochip, which optimizes droplet emission depending on the demand and available storage. Simulation results show significant reduction in latency and reactant usage for mixture preparation.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122341942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Catch your attention: Quality-retaining power saving on mobile OLED displays 吸引您的注意:移动OLED显示屏的保质节能
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593104
Chun-Han Lin, Chih-Kai Kang, P. Hsiu
{"title":"Catch your attention: Quality-retaining power saving on mobile OLED displays","authors":"Chun-Han Lin, Chih-Kai Kang, P. Hsiu","doi":"10.1145/2593069.2593104","DOIUrl":"https://doi.org/10.1145/2593069.2593104","url":null,"abstract":"Organic light-emitting diode (OLED) technology is considered as a promising alternative to mobile displays. This paper explores how to reduce the OLED power consumption by exploiting visual attention. First, we model the problem of OLED image scaling optimization, with the objective of minimizing the power required to display an image without adversely impacting the user's visual experience. Then, we propose an algorithm to solve the fundamental problem, and prove its optimality even without the accurate power model. Finally, based on the algorithm, we consider implementation issues and realize two application scenarios on a commercial OLED mobile tablet. The results of experiments conducted on the tablet with real images demonstrate that the proposed methodology can achieve significant power savings while retaining the visual quality.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123998011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
On using implied values in EDT-based test compression 基于edt的测试压缩中隐含值的使用
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593173
Marcin Gebala, Grzegorz Mrugalski, N. Mukherjee, J. Rajski, J. Tyszer
{"title":"On using implied values in EDT-based test compression","authors":"Marcin Gebala, Grzegorz Mrugalski, N. Mukherjee, J. Rajski, J. Tyszer","doi":"10.1145/2593069.2593173","DOIUrl":"https://doi.org/10.1145/2593069.2593173","url":null,"abstract":"On-chip test compression has quickly established itself as one of the mainstream design-for-test (DFT) methodologies. It assumes that a tester delivers test patterns in a compressed form, and on-chip decompressors expand them into actual data loaded into scan chains. This paper presents a new and comprehensive method to boost performance of sequential test compression and ATPG operations. The approach is primarily aimed at reducing CPU time associated with generating and compressing test patterns. It prevents ATPG from assigning specified values to many inputs in order to cut down a time-consuming backtracking process needed to resolve conflicts leading to compression aborts. The proposed scheme efficiently combines test compression constraints with ATPG. Experimental results obtained for industrial designs illustrate feasibility of the proposed scheme and are reported herein.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127995187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Overlay-aware detailed routing for self-aligned double patterning lithography using the cut process 使用切割工艺的自对准双图案光刻的覆盖感知详细路由
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593176
Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
{"title":"Overlay-aware detailed routing for self-aligned double patterning lithography using the cut process","authors":"Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang","doi":"10.1145/2593069.2593176","DOIUrl":"https://doi.org/10.1145/2593069.2593176","url":null,"abstract":"Self-aligned double patterning (SADP) is one of the most promising techniques for sub-20nm technology. Spacer-is-dielectric SADP using a cut process is getting popular because of its higher design flexibility; for example, it can decompose odd cycles without the need of inserting any stitch. This paper presents the first work that applies the cut process for decomposing odd cycles during routing. For SADP, further, overlay control is a critical issue for yield improvement; while published routers can handle only partial overlay scenarios, our work identifies all the scenarios that induce overlays and proposes a novel constraint graph to model all overlays. With the developed techniques, our router can achieve high-quality routing results with significantly fewer overlays (and thus better yields). Compared with three state-of-the-art studies, our algorithm can achieve the best quality and efficiency, with zero cut conflicts, smallest overlay length, highest routability, and fastest running time.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115909156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Advanced techniques for designing stealthy hardware trojans 设计隐形硬件木马的先进技术
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2596668
N. G. Tsoutsos, Charalambos Konstantinou, M. Maniatakos
{"title":"Advanced techniques for designing stealthy hardware trojans","authors":"N. G. Tsoutsos, Charalambos Konstantinou, M. Maniatakos","doi":"10.1145/2593069.2596668","DOIUrl":"https://doi.org/10.1145/2593069.2596668","url":null,"abstract":"The necessity of detecting malicious modifications in hardware designs has led to the development of various detection tools. Trojan detection approaches aim to reveal compromised designs using several methods such as static code analysis, side-channel dynamic signal analysis, design for testing, verification, and monitoring architectures etc. This paper demonstrates new approaches for circumventing some of the latest Trojan detection techniques. We introduce and implement stealthy Trojans designs that do not violate the functional specifications of the corresponding original models. The designs chosen to demonstrate the effectiveness of our techniques correspond to encryption algorithms and a pseudo random number generator. The proposed Trojans are inserted into the original RTL, and decrease the overall security of the designs, minimizing detection probability by state-of-the-art static analysis tools.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127176347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
System-level floorplan-aware analysis of integrated CPU-GPUs 集成cpu - gpu的系统级平面感知分析
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593225
V. Nandakumar, M. Marek-Sadowska
{"title":"System-level floorplan-aware analysis of integrated CPU-GPUs","authors":"V. Nandakumar, M. Marek-Sadowska","doi":"10.1145/2593069.2593225","DOIUrl":"https://doi.org/10.1145/2593069.2593225","url":null,"abstract":"Conventional, pre-RTL SoC architectural design space exploration does not account for the chip's floorplan. However, the power and performance of integrated CPU-GPUs are highly dependent not only on architectural specifications and workload characteristics but also on the underlying floorplan. We develop a floorplan-aware system-level analysis framework for integrated CPU-GPUs and demonstrate that the overall energy efficiency can be over/under estimated by up to 25% when floorplan is not account-ed for. The floorplan-aware system-level exploration tool allows us to observe interesting dependencies between architectural choices and physical design. These observations guide the frame-work in determining energy efficient floorplans for wide-range of workloads.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126166529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
FALCON: A framework for hierarchical computation of metrics for component-based parameterized SoCs 基于组件的参数化soc的度量层次计算框架
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593138
Haris Javaid, Yusuke Yachide, S. Min, H. Bokhari, S. Parameswaran
{"title":"FALCON: A framework for hierarchical computation of metrics for component-based parameterized SoCs","authors":"Haris Javaid, Yusuke Yachide, S. Min, H. Bokhari, S. Parameswaran","doi":"10.1145/2593069.2593138","DOIUrl":"https://doi.org/10.1145/2593069.2593138","url":null,"abstract":"In this paper, we focus on systematic and efficient computation (accurate value or an estimate) of metrics such as performance, power, energy, etc. of a component-based parameterized system-on-chip (SoC). Traditionally, given models of SoC components (such as cycle-accurate simulator of a processor, trace-based simulator of a cache/memory), a designer manually determines an execution schedule of these models (such as execute processor simulator, followed by cache/memory simulator) to combine/propagate their individual results for computation of a SoC metric. To reduce designer's effort, we propose FALCON, a framework where the execution schedule of component models is generated automatically, and a minimal number of model executions is used to compute values of a SoC metric for the given component models and design space (resulting from component parameter values). FALCON is semi-automated, is applicable to a wide range of SoC platforms with ease, and works with existing design space exploration algorithms. In three case studies (uniprocessor system, multiprocessor pipeline system and multiprocessor mesh network-on-chip system), FALCON reduced designer's effort (measured in minutes) by at least two orders of magnitude.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123672427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信