System-level floorplan-aware analysis of integrated CPU-GPUs

Abstract

Conventional, pre-RTL SoC architectural design space exploration does not account for the chip's floorplan. However, the power and performance of integrated CPU-GPUs are highly dependent not only on architectural specifications and workload characteristics but also on the underlying floorplan. We develop a floorplan-aware system-level analysis framework for integrated CPU-GPUs and demonstrate that the overall energy efficiency can be over/under estimated by up to 25% when floorplan is not account-ed for. The floorplan-aware system-level exploration tool allows us to observe interesting dependencies between architectural choices and physical design. These observations guide the frame-work in determining energy efficient floorplans for wide-range of workloads.