2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献_第2页

Sufficient temporal independence and improved interrupt latencies in a real-time hypervisor 在实时管理程序中充分的时间独立性和改进的中断延迟

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593222

Matthias Beckert, M. Neukirchner, R. Ernst, Stefan M. Petters

引用次数: 12

Robust and in-situ self-testing technique for monitoring device aging effects in pipeline circuits 管道回路中装置老化监测的鲁棒自检测技术

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593205

Jiangyi Li, Mingoo Seok

{"title":"Robust and in-situ self-testing technique for monitoring device aging effects in pipeline circuits","authors":"Jiangyi Li, Mingoo Seok","doi":"10.1145/2593069.2593205","DOIUrl":"https://doi.org/10.1145/2593069.2593205","url":null,"abstract":"Runtime monitoring of aging effects in pipeline circuits is the key to dynamic reliability management techniques which can maximize the performance and energy-efficiency under a reliability envelope without imposing worst-case margin. The existing monitoring techniques are, however, severely limited: for sensor-based techniques, monitoring accuracy is significantly compromised due to the mismatches in aging conditions between sensors and the target circuits, as well as random variation of aging effects; for in-situ techniques, measurement results are sensitive to environmental variations during test phases, also severely reducing monitoring accuracy. We propose a new technique that enables accurate in-situ aging monitoring even under large environmental variations by (i) scaling the supply voltage for temperature-insensitive delay and (ii) reconfiguring target paths into ring oscillators, whose oscillation periods are measured and compared to pre-aging measurement to estimate aging-induced delay degradations. With additional accuracy-improving strategies, the technique achieves highly-accurate monitoring with an error of 15.5% across the temperature variations in self-test phases from 0°C to 80°C, exhibiting >30× improvement in accuracy as compared to the conventional technique operating at nominal supply voltage.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126497637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Simultaneous EUV flare variation minimization and CMP control with coupling-aware dummification 同时极紫外光耀斑变化最小化和耦合感知伪化的CMP控制

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593215

Chi-Yuan Liu, H. Chiang, Yao-Wen Chang, J. H. Jiang

引用次数: 6

Variation aware cache partitioning for multithreaded programs 多线程程序的变化感知缓存分区

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593240

V. Kozhikkottu, Abhisek Pan, Vijay S. Pai, S. Dey, A. Raghunathan

{"title":"Variation aware cache partitioning for multithreaded programs","authors":"V. Kozhikkottu, Abhisek Pan, Vijay S. Pai, S. Dey, A. Raghunathan","doi":"10.1145/2593069.2593240","DOIUrl":"https://doi.org/10.1145/2593069.2593240","url":null,"abstract":"Multithreaded programs are commonly written and optimized for homogeneous multi-core processors assuming equal performance from all the cores. This assumption greatly simplifies the partitioning and balancing of an application's workload across threads; however, it no longer holds when the frequencies of the cores differ due to within-die variations, leading to a degradation in performance. We observe that, in addition to the frequency of the core that it executes on, the performance of a thread is also dependent on the share of shared system resources, such as last-level cache, that it receives. We propose variation-aware cache partitioning as an approach to redress the variation-induced imbalance in the execution times of threads, thereby improving the performance of multi-threaded programs. We discuss the challenges involved in realizing our proposal, including synchronization (e.g., barriers) across threads, which results in faster threads being limited by slower threads, the complex and non-linear relationship between a thread's performance and the cache capacity allocated to it, and the fact that different program phases, can respond quite differently to varying cache capacity. We propose a runtime scheme to perform spatio-temporal cache partitioning while considering both chip characteristics (frequency variations) and program characteristics. We evaluate the proposed technique by applying it to an ensemble of variation-impacted multi-cores executing multi-threaded programs from the PAR-SEC and SPEC-OMP suites, and demonstrate that it results in an average performance improvement of 15% by mitigating the impact of frequency variations.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125432545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

EC-Cache: Exploiting error locality to optimize LDPC in NAND flash-based SSDs EC-Cache:利用错误局部性优化基于NAND闪存的ssd中的LDPC

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593130

Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li

引用次数: 24

Battery management and application for energy-efficient buildings 节能建筑的电池管理与应用

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2596670

Tianshu Wei, Taeyoung Kim, Sangyoung Park, Qidong Zhu, S. Tan, N. Chang, S. Ula, Mehdi Maasoumy

{"title":"Battery management and application for energy-efficient buildings","authors":"Tianshu Wei, Taeyoung Kim, Sangyoung Park, Qidong Zhu, S. Tan, N. Chang, S. Ula, Mehdi Maasoumy","doi":"10.1145/2593069.2596670","DOIUrl":"https://doi.org/10.1145/2593069.2596670","url":null,"abstract":"As the building stock consumes 40% of the U.S. primary energy consumption, it is critically important to improve building energy efficiency. This involves reducing the total energy consumption of buildings, reducing the peak energy demand, and leveraging renewable energy sources, etc. To achieve such goals, hybrid energy supply has becoming popular, where multiple energy sources such as grid electricity, on-site fuel cell generators, solar, wind, and battery storage are scheduled together to improve energy efficiency. In this work, we focus on the application and management of battery storage for energy-efficient buildings. We will first introduce a system-level approach to co-schedule the usage of battery storage (in addition to grid electricity) with the control of building HVAC (heating, ventilation, and air conditioning) system, to reduce the total building energy cost, including the electricity consumption charge, the peak demand charge, and the battery cost. Then, in a separate formulation, we will introduce another system-level study to reduce the energy cost of EV charging and other fixed building energy load through the usage of battery storage and solar PV. Finally, we will present an ARM processor based programmable embedded battery management system (BMS), which monitors battery status, controls charging and discharging at the circuit level, and provides battery protection. The system also works with off-the-shelf battery management IC (Texas Instrument BMS sensor IC) from industry. Comparing to conventional BMS, this software module based BMS is a more suitable solution for energy efficient buildings due to its high flexibility, scalability, and reusability. We will introduce an industrial building testbed with battery storage and solar PV at the University of California, Riverside, and present initial field tests and simulation results for above approaches.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121554705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

Radiation-induced soft error analysis of SRAMs in SOI FinFET technology: A device to circuit approach SOI FinFET技术中sram的辐射诱导软误差分析:器件到电路的方法

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593196

S. Kiamehr, T. Osiecki, M. Tahoori, S. Nassif

引用次数: 22

SLC-enabled wear leveling for MLC PCM considering process variation 考虑工艺变化的MLC PCM的slc支持磨损平衡

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593217

Mengying Zhao, Lei Jiang, Youtao Zhang, C. Xue

引用次数: 58

Design methodologies for 3D mixed signal integrated circuits: A practical 12-bit SAR ADC design case 三维混合信号集成电路的设计方法:一个实用的12位SAR ADC设计案例

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593122

Wulong Liu, Guoqing Chen, Xuefeng Han, Yu Wang, Yuan Xie, Huazhong Yang

{"title":"Design methodologies for 3D mixed signal integrated circuits: A practical 12-bit SAR ADC design case","authors":"Wulong Liu, Guoqing Chen, Xuefeng Han, Yu Wang, Yuan Xie, Huazhong Yang","doi":"10.1145/2593069.2593122","DOIUrl":"https://doi.org/10.1145/2593069.2593122","url":null,"abstract":"Three-dimensional (3D) integration technology has been proposed as a promising technology to provide small footprint, reduced wire-length, and the capability of heterogeneous integration. In particular, 3D IC is a good candidate to address the design issues in conventional analog/digital mixed-signal IC designs. In this work, we focus on modeling and analyzing the impacts of through silicon vias (TSVs) on mixed-signal ICs. Based on the analysis, a set of design methodologies for 3D mixed-signal ICs are proposed. The design methodologies are verified with a case study, in which a 12-bit successive approximation register analog-to-digital converter (SAR ADC) is re-designed by partitioning it into three stacked layers for 3D integration. The experimental results show that, compared to the traditional 2D counterpart, our 3D SAR ADC with optimized TSV placement can achieve significant area and power reduction, and performance improvement. Specifically, due to the isolation of substrate noise disturbance in our 3D design, the signal-to-noise-plus-distortion ratio (SNDR) is improved from 68.74 dB to 74.12 dB.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134177827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Practical functional and washing droplet routing for cross-contamination avoidance in digital microfluidic biochips 数字微流控生物芯片中避免交叉污染的实用功能和洗涤液滴路径

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2014-06-01 DOI: 10.1145/2593069.2593189

Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai

引用次数: 23