Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)最新文献

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Micro-mechanical characterizations of solder mask materials 阻焊材料的微观力学特性
Hau Zhu, Yifan Guo, Wen-Ying Li, A. Tseng, B. Martin
{"title":"Micro-mechanical characterizations of solder mask materials","authors":"Hau Zhu, Yifan Guo, Wen-Ying Li, A. Tseng, B. Martin","doi":"10.1109/EPTC.2000.906364","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906364","url":null,"abstract":"The mechanical properties of solder masks are critical in the reliability performance of flip-chip packages. Many recent studies show that the mechanical properties of solder mask materials have great influence on moisture absorption, delamination at interconnections and solder fatigue life in flip-chip packages. There are also assembly process issues related to the properties of solder masks. This article presents an experimental investigation that mechanically characterizes two polyimide solder mask materials, type A and type B, by using a micro thermo-mechanical tester. The mask samples are prepared as thin film specimens. Mechanical properties such as Young's modulus, failure strength and creep behaviors are determined based on the recorded data from the experiments. In addition, a testing procedure for measuring the coefficient of thermal expansion (CTE) is developed, which provides an alternative to the TMA method. It is shown that the experimental investigation is suitable in conducting such a characterization of thin-film solder masks.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116904421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Board level reliability testing of /spl mu/BGA/sup (R)/ packaging with lead-free solder attachment 电路板级可靠性测试/spl mu/BGA/sup (R)/封装无铅焊料附件
V. Solberg
{"title":"Board level reliability testing of /spl mu/BGA/sup (R)/ packaging with lead-free solder attachment","authors":"V. Solberg","doi":"10.1109/EPTC.2000.906342","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906342","url":null,"abstract":"To maximize the benefit of chip-scale packaging for portable and handheld electronics, the user must consider efficient and cost effective assembly processing. Factors that an engineer should review before developing the product using CSP may include physical features and construction of the device, environmental limitations, suitable substrate materials and a general understanding of the attachment methodology. Many of the electronic products being developed using miniature chip-scale packages are moving toward lead-free, environmentally safe assembly processes. This paper reviews chip-size flash and RAMBUS memory test device applications utilizing /spl mu/BGA/sup (R)/ package technology, explore alternative solder alloy compositions, furnish recommendations for solder process temperature profiles and present the results from extensive thermal cycle testing, comparing eutectic solder to lead-free solder ball contacts and attachment materials.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116905406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The reliability performance of low cost bumping on aluminum and copper wafer 铝和铜晶片低成本碰撞的可靠性性能
R. Uang, Kuo-Chuan Chen, Szu-wei Lu, Hsun Hu, S. Huang
{"title":"The reliability performance of low cost bumping on aluminum and copper wafer","authors":"R. Uang, Kuo-Chuan Chen, Szu-wei Lu, Hsun Hu, S. Huang","doi":"10.1109/EPTC.2000.906389","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906389","url":null,"abstract":"A low cost bumping technology for semiconductor chips is described here using electroless Ni/Au plating for under bump metallurgy (UBM) formation, instead of traditional processes involving sputtering, photolithography, and etching which require a great deal of expensive equipment. Higher throughput and lower cost can be achieved if we combine electroless Ni/Au technology and stencil solder printing technology. Low cost bumping technology has been successfully developed on Al wafers. The results of reliability tests, such as high temperature storage, temperature cycling and temperature-humidity storage, show that solder bumps with electroless Ni/Au as UBM exhibit good reliability and are suitable for flip-chip applications. In addition to electroless Ni/Au plating on Al pads, the development of low cost bumping on Cu wafers is also presented in this paper. The performance of Ni/Au bumps on copper, such as morphology and shear strength, is superior to that on Al pads. The reliability tests of low cost solder bumps were also performed on dummy copper wafers that consist of sputtered Cu and PI passivation. Comparisons were also made of the reliability performance of low cost solder bumps on aluminum and copper pads in this paper.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124051404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An experimental procedure to derive reliable IBIS models 导出可靠IBIS模型的实验程序
T. Zák, M. Ducrot, C. Xavier, M. Drissi
{"title":"An experimental procedure to derive reliable IBIS models","authors":"T. Zák, M. Ducrot, C. Xavier, M. Drissi","doi":"10.1109/EPTC.2000.906397","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906397","url":null,"abstract":"One of the greater parts of PCB research and development is to manage the electromagnetic compatibility and signal integrity (EMC/SI) constraints. However, the performances of these EMC/SI tools are based on the quality of used library models: PCB interconnections and IBIS models (I/O buffer information specification). To obtain an IBIS model, three methods are possible: the component maker using the Web, SPICE conversion if the corresponding SPICE model is available, and measurements. This paper describes an experimental procedure that allows creation of reliable IBIS model version 2.1 from measurements. This procedure allows building of models using classical measurement devices, controlling all steps of the procedure and achieving the required model accuracy with regard to its application field. To check the accuracy of the developed procedure, the paper presents the characterization of a TQFP component. Through a classical SI phenomenon (reflection), comparison between measured and simulated results is performed, using the available IBIS Web model and the measured IBIS model.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115769766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Correlation of underfill viscosity and contact angle on surfaces in a flip chip package 倒装芯片封装表面上的下填料粘度与接触角的相关性
Ho Pei Sze, I. Rasiah, G. Chew
{"title":"Correlation of underfill viscosity and contact angle on surfaces in a flip chip package","authors":"Ho Pei Sze, I. Rasiah, G. Chew","doi":"10.1109/EPTC.2000.906371","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906371","url":null,"abstract":"Flip-chip packages can achieve high interconnect speeds, high-density and be made in thinner dimensions. Despite these advantages, the demand for flip-chip packages is still relatively low when compared to packages using wire bonding. This is due to the requirement for bumped dice for these packages as well as capital expenditure for new equipment dedicated to flip chip packaging. In any case, the positive benefits are expected to drive the industry towards flip chip technology and are expected to take off and grow in the years to come. As this happens, problems unique to flip chip packaging are set to emerge. Unlike traditional packaging, flip chip packaging has more interfaces that are interacting with one another. The ability of these interfaces to stay reliable under various stress conditions is critical to the success of the package. One material that has more interfaces to contend with then any other material within the flip chip package is the underfill. The interfaces that the underfill attaches to include the die surface, solder bump and the solder mask. This paper looks at the change of contact angle over time for three underfills on the die and the solder mask surfaces. This change is also measured for varying temperatures. This is then correlated with the underfill viscosity at those temperatures. Certain time and temperature based relationships are derived. The properties of the three underfills are also discussed and their performance for varying durations in humidity and thermal shock cycling are analyzed.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134356248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Interdiffusion between Cu and Sn-rich solder: dominant diffusion species 富锡钎料与Cu钎料间的互扩散:主要扩散物质
Si-Jung Kim, K. Bae
{"title":"Interdiffusion between Cu and Sn-rich solder: dominant diffusion species","authors":"Si-Jung Kim, K. Bae","doi":"10.1109/EPTC.2000.906353","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906353","url":null,"abstract":"Extensive microstructural and kinetic studies on the formation and growth of the intermetallics of Sn-rich solder/Cu couples have been reported. However, experimental data on the dominant diffusing species are limited and in conflict. The dominant diffusing species for the soldering and aging of Sn-3.5Ag alloy/Cu couples were investigated by using an unsoldered or Cr-evaporated surface as a reference line. After soldering, the Sn-rich alloy on top of the scallop-shaped Cu/sub 6/Sn/sub 5/ intermetallic compound was observed below the original Cu surface. Sn was also observed to diffuse to Cu during the aging process. Therefore, Sn was suggested to be the dominant diffusing species for both soldering and aging.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132740426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A comparative study of different plane modelling methodologies for high density electronic packages 高密度电子封装不同平面建模方法的比较研究
Y. Yeo, Shih-Yen Lee, M. Iyer, M. Leong
{"title":"A comparative study of different plane modelling methodologies for high density electronic packages","authors":"Y. Yeo, Shih-Yen Lee, M. Iyer, M. Leong","doi":"10.1109/EPTC.2000.906375","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906375","url":null,"abstract":"There are various methods to model a power and ground plane pair found in the power distribution networks of IC packages and printed circuit boards. In this paper, three such methods are examined. The simulation results are compared with measurements and the relative merits and drawbacks of these methods are discussed.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115233128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A methodology for predicting failure sites and failure modes in an IC package 预测IC封装中失效位置和失效模式的方法
A. Tay, K. Lee, W. Zhou, K. Lim
{"title":"A methodology for predicting failure sites and failure modes in an IC package","authors":"A. Tay, K. Lee, W. Zhou, K. Lim","doi":"10.1109/EPTC.2000.906385","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906385","url":null,"abstract":"A methodology for predicting sites and modes of thermomechanical failure in an IC package is developed. Singular stress fields around several stress concentration locations in a typical plastic-encapsulated IC package are calculated using special variable-order singular boundary elements and the singular value decomposition method. The strain energy density distributions around all the stress concentration locations are then obtained from the singular stress fields and compared. The most likely failure site as the temperature of the package is raised is then determined as well as the likely failure modes, i.e. interfacial delamination or cracking of mold compound.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124074315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Electrical and thermal modelling of QFN packages QFN封装的电气和热建模
A. Lu, D. Xie, Z. Shi, W. Ryu
{"title":"Electrical and thermal modelling of QFN packages","authors":"A. Lu, D. Xie, Z. Shi, W. Ryu","doi":"10.1109/EPTC.2000.906399","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906399","url":null,"abstract":"The quad flat no lead or QFN package, a near CSP leadframe, is a promising choice for portable wireless applications such as Bluetooth/sup TM/ and home RF. Attractive attributes of this advanced package include miniaturised footprint, good electrical performance and excellent thermal characteristics. The paper describes electrical and thermal modelling techniques as part of an integrated performance validation methodology for a typical 32 I/O (0.5 mm pitch) QFN package structure. It is shown how electromagnetic simulations can be used effectively to explore the design space during the QFN development cycle. Results from parametric studies on the impact of die shrink and bond wire profile are presented. A two-layer 48 I/O fine pitch (0.5 mm pitch) BGA package is also included to provide a comparison of electrical and thermal performance.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125984590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Applications of a 3-D field solver for on-chip and package microstrip interconnection design 三维现场求解器在片上和封装微带互连设计中的应用
Woonghwan Ryu, A. Wai, Fan Wei, Joungho Kim
{"title":"Applications of a 3-D field solver for on-chip and package microstrip interconnection design","authors":"Woonghwan Ryu, A. Wai, Fan Wei, Joungho Kim","doi":"10.1109/EPTC.2000.906373","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906373","url":null,"abstract":"Accurate electronics package design is required for high-performance RF and GHz interconnections to minimize undesirable electromagnetic wave phenomena and to maximize the transmission bandwidth. Hence, prediction of electrical performance of the microstrip line, essential even in ICs, is needed for efficient microstrip design and analysis. In this paper, an accurate and efficient design methodology for GHz IC and package microstrip interconnections is proposed. In this analysis, three commercial software tools have been used and compared: three-dimensional (3D) electromagnetic (EM) field solver, a planar 3D (2.5D) EM field solver, and a transmission line calculator based on analytical solutions. Also, for 5% error between the 3D EM field solver and the 2.5D EM field solver, the ratio of metal thickness (T)-to-dielectric height (H) considering fringing fields, dispersion effects, and radiation loss has been found to be more than 0.1 for a relatively wide microstrip line (signal line width (W)-to-dielectric height (H) ratio /spl ges/1). Consequently, this work presents a contribution to accurate and efficient design for high-frequency on-chip and package interconnections. We also study the comparison of EM solving and experimental approaches for on-chip embedded microstrip interconnection design.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126121913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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