Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)最新文献

Micro-mechanical characterizations of solder mask materials 阻焊材料的微观力学特性

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906364

Hau Zhu, Yifan Guo, Wen-Ying Li, A. Tseng, B. Martin

引用次数: 14

Board level reliability testing of /spl mu/BGA/sup (R)/ packaging with lead-free solder attachment 电路板级可靠性测试/spl mu/BGA/sup (R)/封装无铅焊料附件

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906342

V. Solberg

引用次数: 3

The reliability performance of low cost bumping on aluminum and copper wafer 铝和铜晶片低成本碰撞的可靠性性能

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906389

R. Uang, Kuo-Chuan Chen, Szu-wei Lu, Hsun Hu, S. Huang

{"title":"The reliability performance of low cost bumping on aluminum and copper wafer","authors":"R. Uang, Kuo-Chuan Chen, Szu-wei Lu, Hsun Hu, S. Huang","doi":"10.1109/EPTC.2000.906389","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906389","url":null,"abstract":"A low cost bumping technology for semiconductor chips is described here using electroless Ni/Au plating for under bump metallurgy (UBM) formation, instead of traditional processes involving sputtering, photolithography, and etching which require a great deal of expensive equipment. Higher throughput and lower cost can be achieved if we combine electroless Ni/Au technology and stencil solder printing technology. Low cost bumping technology has been successfully developed on Al wafers. The results of reliability tests, such as high temperature storage, temperature cycling and temperature-humidity storage, show that solder bumps with electroless Ni/Au as UBM exhibit good reliability and are suitable for flip-chip applications. In addition to electroless Ni/Au plating on Al pads, the development of low cost bumping on Cu wafers is also presented in this paper. The performance of Ni/Au bumps on copper, such as morphology and shear strength, is superior to that on Al pads. The reliability tests of low cost solder bumps were also performed on dummy copper wafers that consist of sputtered Cu and PI passivation. Comparisons were also made of the reliability performance of low cost solder bumps on aluminum and copper pads in this paper.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124051404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

An experimental procedure to derive reliable IBIS models 导出可靠IBIS模型的实验程序

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906397

T. Zák, M. Ducrot, C. Xavier, M. Drissi

引用次数: 15

Correlation of underfill viscosity and contact angle on surfaces in a flip chip package 倒装芯片封装表面上的下填料粘度与接触角的相关性

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906371

Ho Pei Sze, I. Rasiah, G. Chew

{"title":"Correlation of underfill viscosity and contact angle on surfaces in a flip chip package","authors":"Ho Pei Sze, I. Rasiah, G. Chew","doi":"10.1109/EPTC.2000.906371","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906371","url":null,"abstract":"Flip-chip packages can achieve high interconnect speeds, high-density and be made in thinner dimensions. Despite these advantages, the demand for flip-chip packages is still relatively low when compared to packages using wire bonding. This is due to the requirement for bumped dice for these packages as well as capital expenditure for new equipment dedicated to flip chip packaging. In any case, the positive benefits are expected to drive the industry towards flip chip technology and are expected to take off and grow in the years to come. As this happens, problems unique to flip chip packaging are set to emerge. Unlike traditional packaging, flip chip packaging has more interfaces that are interacting with one another. The ability of these interfaces to stay reliable under various stress conditions is critical to the success of the package. One material that has more interfaces to contend with then any other material within the flip chip package is the underfill. The interfaces that the underfill attaches to include the die surface, solder bump and the solder mask. This paper looks at the change of contact angle over time for three underfills on the die and the solder mask surfaces. This change is also measured for varying temperatures. This is then correlated with the underfill viscosity at those temperatures. Certain time and temperature based relationships are derived. The properties of the three underfills are also discussed and their performance for varying durations in humidity and thermal shock cycling are analyzed.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134356248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Interdiffusion between Cu and Sn-rich solder: dominant diffusion species 富锡钎料与Cu钎料间的互扩散:主要扩散物质

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906353

Si-Jung Kim, K. Bae

引用次数: 4

A comparative study of different plane modelling methodologies for high density electronic packages 高密度电子封装不同平面建模方法的比较研究

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906375

Y. Yeo, Shih-Yen Lee, M. Iyer, M. Leong

引用次数: 4

A methodology for predicting failure sites and failure modes in an IC package 预测IC封装中失效位置和失效模式的方法

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906385

A. Tay, K. Lee, W. Zhou, K. Lim

引用次数: 5

Electrical and thermal modelling of QFN packages QFN封装的电气和热建模

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906399

A. Lu, D. Xie, Z. Shi, W. Ryu

引用次数: 25

Applications of a 3-D field solver for on-chip and package microstrip interconnection design 三维现场求解器在片上和封装微带互连设计中的应用

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456) Pub Date : 2000-12-05 DOI: 10.1109/EPTC.2000.906373

Woonghwan Ryu, A. Wai, Fan Wei, Joungho Kim

{"title":"Applications of a 3-D field solver for on-chip and package microstrip interconnection design","authors":"Woonghwan Ryu, A. Wai, Fan Wei, Joungho Kim","doi":"10.1109/EPTC.2000.906373","DOIUrl":"https://doi.org/10.1109/EPTC.2000.906373","url":null,"abstract":"Accurate electronics package design is required for high-performance RF and GHz interconnections to minimize undesirable electromagnetic wave phenomena and to maximize the transmission bandwidth. Hence, prediction of electrical performance of the microstrip line, essential even in ICs, is needed for efficient microstrip design and analysis. In this paper, an accurate and efficient design methodology for GHz IC and package microstrip interconnections is proposed. In this analysis, three commercial software tools have been used and compared: three-dimensional (3D) electromagnetic (EM) field solver, a planar 3D (2.5D) EM field solver, and a transmission line calculator based on analytical solutions. Also, for 5% error between the 3D EM field solver and the 2.5D EM field solver, the ratio of metal thickness (T)-to-dielectric height (H) considering fringing fields, dispersion effects, and radiation loss has been found to be more than 0.1 for a relatively wide microstrip line (signal line width (W)-to-dielectric height (H) ratio /spl ges/1). Consequently, this work presents a contribution to accurate and efficient design for high-frequency on-chip and package interconnections. We also study the comparison of EM solving and experimental approaches for on-chip embedded microstrip interconnection design.","PeriodicalId":430941,"journal":{"name":"Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126121913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5