{"title":"Low Power Implementation of ECG R-wave Peak Detector in 180 nm CMOS Process","authors":"Deepa Kota, N. Tasneem, I. Mahbub","doi":"10.1109/DCAS51144.2020.9330635","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330635","url":null,"abstract":"With the widespread use of sensor technology, monitoring heart conditions is feasible and widely accessible. Electrocardiogram (ECG) signals contain rich information concerning several heart diseases including sudden cardiac arrests (SCAs). Continuous monitoring of heartbeat using wearable devices can help detect heart irregularities. While current wearable devices transmit raw ECG signals for processing, this paper proposes a novel on-chip ECG feature extraction system implemented on standard 180 nm CMOS technology using the Cadence Virtuoso tool. The proposed design detects all peaks with a high degree of sensitivity compared to earlier systems. Future enhancements of the design will include the determination of the R to R interval. The total power consumption for the design is just 0.379 nW, which is much lower in comparison to other implementations. This design has been verified on ECG data acquired from live subjects in a lab environment. In addition, the design is also verified on Physionet, an archive of well-characterized ECG databases collected from healthy subjects while exercising. Two datasets are tested into this design to check for peak detection and heart rate abnormality.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127761675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ternary Limited-Weight Codes and Quaternary Transition-Signaling for Low-Power Bus Encoding","authors":"Maryam Sadat Hosseini Omshi, R. F. Mirzaee","doi":"10.1109/DCAS51144.2020.9330656","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330656","url":null,"abstract":"This paper presents a new bus encoding scheme by ternary limited-weight codes (ternary LWC) and quaternary transition-signaling for low-power, high-performance data transmission. In this technique, digit ‘0’ indicates no transition, whereas ‘1’ and ‘2’ indicate two different types of transitions within a clock cycle. The number of ternary LWC code words as well as their length and weight affect the overall performance of the bus system. On the one hand, it is preferred to have fewer ‘1's and ‘2's in order to decrease the switching activity factor. On the other hand, shorter code words reduce the amount of redundancy. The mathematical analyses reveal that 64 4-digit ternary LWC code words with the maximum weight of three is the optimal solution, considering other criteria. Furthermore, our estimations show promising results, including 22.4% and 50.3% average reductions in switching activity and voltage swing, respectively. Therefore, the proposed bus encoding technique can reduce dynamic power up to 80.8%. In addition, it increases data transmission rate by the factor of 1.5.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133788263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Low-Power Front-End with Compressive Sensing Circuit for Neural Signal Acquisition Designed in 180 nm CMOS Process","authors":"Karthik Kakaraparty, N. Tasneem, I. Mahbub","doi":"10.1109/DCAS51144.2020.9330674","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330674","url":null,"abstract":"Multi-channel data acquisition of bio-signals is a promising technology that is being used in many fields these days. Compressed sensing (CS) is an innovative approach of signal processing that facilitates sub-Nyquist processing of bio-signals, such as an electrocardiogram (ECG) and electroencephalogram (EEG). This strategy can be used to lower the data rate to realize ultra-low-power performance, As the count of recording channels increase, data volume is increased resulting in impermissible transmitting power. This paper presents the implementation of a CMOS-based front-end design with the CS in the standard 180 nm CMOS process. A novel pseudo-random sequence generator is proposed, which consists of two different types of D flip-flops that are used for obtaining a completely random sequence. The power consumed by the bio-signal amplifier block is 2.35 μW. The SAR-ADC block that is designed to digitize the amplified signal consumes 277 μW of power and the power consumption value of the pseudo-random bit sequence generator (PRBS) is 344.2μW. The sampling rate of PRBS block is 611.76 Kbps. We have considered collecting neural data from the 32 channels, and achieved an 8.5X compression rate. The low power consumption per channel confirms the importance of the proposed approach for multiple channel high-density neural interfaces.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128211305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study the Effects of Misalignments in the Printed Spiral Inductive Coils for Passive Wearable Sensors","authors":"B. Noroozi, B. Morshed","doi":"10.1109/DCAS51144.2020.9330661","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330661","url":null,"abstract":"Inductive coupling between two coils is becoming an important technique for wireless power and data transfer in near-field for a variety of applications such as wireless charging and passive (zero-power) sensors. We have previously employed a pair of printed spiral coils (PSC) to collect the physiological signals via our novel Wireless Resistive Analog Passive (WRAP) skin attachable sensors. The pair of PSCs and the circuit components have been optimized to maximize the probed biosignals where the mutual inductance (or coupling factor) was kept constant. However, the coils' relative positions in the wearables can vary in real-life scenarios, which makes the mutual inductance to change, compromising optimal results. To design a system with maximum robustness against these PSC alignment variations, the effects of primary coil size on the coupling factor variability to axial and lateral displacements are studied. We limited the maximum self-inductance to 5 µH and 7 µH for primary and secondary coils, respectively that ensures the results are not affected by the coils' self-inductance variation. Our simulation shows that larger primary coils create magnetic fields with reduced sensitivity to the coupling factor for lateral and axial displacements. The resultant coupling factor behavior indicates robust coil designs for applications where the axial and lateral displacements can occur in real-life.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115889903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Advanced Non-linear Control Technique for Current-Fed Full-Bridge DC-DC Converter","authors":"Sameer Arora, P. Balsara, D. Bhatia","doi":"10.1109/DCAS51144.2020.9330650","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330650","url":null,"abstract":"Boost and boost derived DC-DC converters exhibit the phenomenon of unstable zero dynamics. This leads to zero in the right-half of the s-plane, thereby making the DC-DC converters bandlimited. Applying advanced control techniques that require system inversion to cancel the non-linearities cannot be implemented since a zero in right-half plane leads to a right-half plane pole which is not a feasible pole-zero cancellation. This paper proposes a non-linear inversion control technique which implements an output re-definition technique to design a controller for a non-minimum phase system. The paper uses an example of boost derived full-bridge (current-fed) DC-DC converter. The paper models and analyzes the zero dynamics and discusses the method used to stabilize the zero dynamics. Further, input-output feedback linearization control is implemented deriving the control law. Simulation results are presented, where detailed analysis shows the proposed technique offers multiple advantages.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"708 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126787819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sara Akbarzadeh, N. Alamdari, Christina Campbell, E. Lobarinas, N. Kehtarnavaz
{"title":"Word Recognition Clinical Testing of Personalized Deep Reinforcement Learning Compression","authors":"Sara Akbarzadeh, N. Alamdari, Christina Campbell, E. Lobarinas, N. Kehtarnavaz","doi":"10.1109/DCAS51144.2020.9330640","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330640","url":null,"abstract":"Current hearing aid fittings are carried out using prescriptive compression settings. These settings are derived from group averages but do not account for individual differences or preferences. In a previous work, we developed a human-in-the-loop deep reinforcement learning compression approach to set the compression ratios across a number of frequency bands. These compression ratios were compared to those of the widely used and accepted DSL-v5 hearing aid prescription to determine if incorporating user preference impacted word recognition performance. A pilot clinical study of this comparison for four participants is reported in this paper. The clinical testing results obtained strongly support the hypothesis that the personalized compression settings do not negatively impact word recognition or audibility compared to the prescriptive compression settings. The ability to provide a personalized amplification strategy with no degradation in hearing performance would be of benefit in hearing aids or other assistive listening technologies.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"73 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130782669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Linearity Enhancement Using a Common-Drain Topology for Envelope Tracking CMOS Power Amplifiers","authors":"Sumit Bhardwaj, S. Moallemi, J. Kitchen","doi":"10.1109/DCAS51144.2020.9330649","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330649","url":null,"abstract":"This work discusses about the linearity challenges of a radio frequency power amplifier (RF-PA) using envelope tracking (ET) technique. ET modulators vary the supply voltage of a PA to improve its efficiency, but also add undesired ripple at the supply node which affect the PA's linearity. Also, device non-linearities of the PA add distortion to the transmitted signal and degrade its spectral purity. To overcome the aforementioned issues, a fully differential common-drain architecture for the PA is proposed and linearity enhancement is demonstrated in TSMC CMOS 65 nm technology.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115646458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ACPA: Exploiting Approximate Computing for High-Level Imprecision Optimization of Fixed-point LTI systems","authors":"Mahdieh Grailoo, B. Alizadeh, T. Nikoubin","doi":"10.1109/DCAS51144.2020.9330657","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330657","url":null,"abstract":"The high-level imprecision optimization (HLIO) is a design paradigm in a wide variety of error-resilient digital signal processing (DSP) systems to decrease the hardware cost within an acceptable deviation from the nominal output values. In these systems, Approximate computing (AC) has emerged as the new design paradigm, which has the common goal of designing efficient systems by trading accuracy for hardware cost with HLIO. In this paper, we make use of AC as a complementary paradigm in HLIOs to improve the utilization of the error budget compared to existing HLIOs with the aim of further reduction in the area and delay. So, we improve HLIO using AC on fixed-point implementation of a feed-forward linear-time-invariant (LTI) system, when the error measure budget is specified as maximum mismatch (MM), or maximum absolute error. The results show that our method can improve the area by 21% and delay by 9.3% on average compared to the state-of-the-art techniques.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133000987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a Dynamic Parameter-Controlled Chaotic-PRNG in a 65 nm CMOS process","authors":"P. Paul, Maisha Sadia, Md. Sakib Hasan","doi":"10.1109/DCAS51144.2020.9330647","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330647","url":null,"abstract":"In this paper, we present the design of a new chaotic map circuit with a 65 nm CMOS process. This chaotic map circuit uses a dynamic parameter-control topology and generates a wide chaotic range. We propose two designs of dynamic parameter-controlled chaotic map (DPCCM)-based pseudo-random number generators (PRNG). The randomness of the generated sequence is verified using three different statistical tests, namely, NIST SP 800–22 test, FIPS PUB 140–2 test, and Diehard test. Our first design offers a throughput of 200 MS/s with an on-chip area of 0.024 mm2 and a power consumption of 2.33 mW. The throughput of our second design is 300 MS/s with an area consumption of 0.132 mm2 and power consumption of 2.14 mW. The wider chaotic range and lower-overhead, offered by our designs, can be highly suitable for various applications such as, logic obfuscation, chaos-based cryptography, re-configurable random number generation, and hard-ware security for resource-constrained edge devices like IoT.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134472544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Broadband Class AB Power Amplifier with Second Harmonic Injection","authors":"Pouria Pazhouhesh, J. Kitchen","doi":"10.1109/dcas51144.2020.9330364","DOIUrl":"https://doi.org/10.1109/dcas51144.2020.9330364","url":null,"abstract":"This work presents a broadband class AB push-pull power amplifier with second harmonic injection, where the second harmonic is injected through the center tap of an even harmonic trap to improve the class AB push-pull efficiency over an octave of bandwidth. The PA is designed and simulated in a 65 nm CMOS technology, and exhibits greater than 22.7% PAE from 2 GHz to 6.7 GHz at an average saturated output power of 22 dBm over the entire band. At saturated output power, the maximum PAE improves by 2.5% compared to the conventional push-pull class AB. The PA's gain is 12 dB, with input return loss better than -10 dB from 2 to 6.7 GHz, resulting in a 108% fractional bandwidth.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132775384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}