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Study on impact of process on Bitcell design in FinFets 工艺对finfet中Bitcell设计的影响研究
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/DCAS51144.2020.9330648
M. Anees, K. Rahul, Santosh Yachareni, Sourabh Aditya Swarnkar
{"title":"Study on impact of process on Bitcell design in FinFets","authors":"M. Anees, K. Rahul, Santosh Yachareni, Sourabh Aditya Swarnkar","doi":"10.1109/DCAS51144.2020.9330648","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330648","url":null,"abstract":"This paper discusses the impact of process scaling on bitcells in FinFets on 7nm and beyond. Every new process node is targeted to shrink the size of transistors. Shrinking in size makes the device vulnerable to process variations. The impact of the process variations creates new design challenges. Bitcells being at the forefront of every new process nodes face all-new levels of design complexity both in terms of the fabrication process and in designing. Bitcells are placed in every chip and the density of the same keeps growing. In the 7nm process, transistor density reaches approximately 96.5M Tr/mm2 with a bitcell dimension of 0.027um2. Moving towards 3nm, number of transistors could increase by 40%-50% for the same area, because of 2-fin minimum usage requirement. Having correct contingency circuits to fix failing bitcells is very important. The contingency circuits can be read assist, write assist circuits. As supply voltage is reduced, it is reaching towards the threshold voltage. Reduction in voltage to reduce the power only aggravates the problem. This requires an understanding of the impact of the process on bitcell qualifying parameters. This paper shows how the process is impacting the bitcells and its impact can be seen by measuring the bitcells qualifying parameters.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129236783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of an active-filtering circuit for electroencephalographic signal acquisition using an 8-bit microcontroller 用8位微控制器实现脑电图信号采集有源滤波电路
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/DCAS51144.2020.9330655
José Pérez, Jimmy Tarrillo
{"title":"Implementation of an active-filtering circuit for electroencephalographic signal acquisition using an 8-bit microcontroller","authors":"José Pérez, Jimmy Tarrillo","doi":"10.1109/DCAS51144.2020.9330655","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330655","url":null,"abstract":"Electroencephalographic signals are employed to analyze brain activity. By being low voltage level signals, its digitalization represents a big challenge. Currently, there are several proposals and BCIs, many of them based on complicated and expensive ADCs and DSPs to collect and digitally process data. Hence, this paper presents the design and implementation of an active-filtering circuit for electroencephalographic signal acquisition in a frequency range between 0.15 Hz and 50Hz using an 8-bit AVR RISC-based microcontroller. This hardware is composed of four fundamental elements: Reception block, filtering circuit, ADC adaptation circuit, and digital communication system. This paper offers the results of board design, emulation, and implementation concerning the amplitude spectrum and its SNR value.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"147 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128948311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Miniaturized Highly Efficient Headstage Based Wireless Power Transfer (WPT) System for Optogenetic Stimulation of Freely Moving Animals 一种用于自由运动动物光遗传刺激的小型高效头台无线能量传输系统
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/DCAS51144.2020.9330642
D. Biswas, Jose H. A Martinez, Ishani Kaul, Arnav Kaul, I. Mahbub
{"title":"A Miniaturized Highly Efficient Headstage Based Wireless Power Transfer (WPT) System for Optogenetic Stimulation of Freely Moving Animals","authors":"D. Biswas, Jose H. A Martinez, Ishani Kaul, Arnav Kaul, I. Mahbub","doi":"10.1109/DCAS51144.2020.9330642","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330642","url":null,"abstract":"For the treatment of chronic neuropathic diseases, long-term behavior study of the patient is very important. The behavior study is performed using neural stimulation and simultaneously recording the response from the neural cells. Headstage-based neuromodulation device has become one of the popular methods for neural stimulation in recent times. In this work, a wirelessly powered system is presented that provides constant power to a headstage based optogenetic stimulator, which includes a receiver (RX) coil, a rectifier, and an mm-sized light-emitting-diode (LED). A multi-layered transmitter (TX) coil is designed to provide uniform power transmission over the 20.7 cm × 14 cm mouse behavioral cage area. A maximum of ~49% efficiency is achieved using the proposed system at 3 cm distance through the air media at 13.56 MHz operating frequency. The proposed system uses less number of headstage resonators on the 3-D printed light-weight headstage which is able to achieve higher efficiency compared to the other state-of-the-art.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114278439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference DCAS 2020 2020年IEEE达拉斯电路与系统会议论文集DCAS 2020
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/dcas51144.2020.9330641
{"title":"Proceedings of the 2020 IEEE Dallas Circuits and Systems Conference DCAS 2020","authors":"","doi":"10.1109/dcas51144.2020.9330641","DOIUrl":"https://doi.org/10.1109/dcas51144.2020.9330641","url":null,"abstract":"","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124894668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Robust Implementation of Memristive Reservoir Computing with Crossbar Based Readout Layer 基于横条读出层的记忆性油藏计算鲁棒实现
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/DCAS51144.2020.9330367
Sagarvarma Sayyaparaju, Mst Shamim Ara Shawkat, G. Rose
{"title":"Robust Implementation of Memristive Reservoir Computing with Crossbar Based Readout Layer","authors":"Sagarvarma Sayyaparaju, Mst Shamim Ara Shawkat, G. Rose","doi":"10.1109/DCAS51144.2020.9330367","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330367","url":null,"abstract":"Reservoir computing (RC) is a neural network paradigm that aims to significantly reduce the training cost of recurrent neural networks. Physical reservoir computing is the hardware realization of this system that aims to achieve faster data processing with low training costs. This paper presents a robust memristor-based liquid state machine implementation of reservoir computing. A generalized hardware framework for this system's implementation is proposed that can be used to realize any given network topology. Also, a readout layer based on simple spike-timing-dependent plasticity (STDP) based online learning is proposed for the system. Such an implementation will lead to reduced training cost for the system. Additionally, this readout layer is shown to be robust against device level switching asymmetries that are prevalent in contemporary memristor devices.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116535883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map 基于G4FET-NDR离散映射的增强可重构混沌振荡器设计
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/DCAS51144.2020.9330653
Md. Sakib Hasan, A. S. Shanta, P. Paul, Maisha Sadia, M. Majumder, G. Rose
{"title":"Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map","authors":"Md. Sakib Hasan, A. S. Shanta, P. Paul, Maisha Sadia, M. Majumder, G. Rose","doi":"10.1109/DCAS51144.2020.9330653","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330653","url":null,"abstract":"In this paper, a novel chaotic map is introduced using a voltage controlled negative differential resistance (NDR) circuit composed of an n-channel and a p-channel silicon-on-insulator (SOI) four-gate transistor (G4FET). The multiple gates of the G4FET are leveraged to create a discrete chaotic map with three bifurcation parameters. The three tunable parameters are the gain of a transimpedance amplifier (TIA), top-gate voltage of n- channel G4FET, and top-gate voltage of p-channel G4FET. Two methods are proposed for building chaotic oscillators using this discrete map. The effect of altering bifurcation parameters on chaotic operation is illustrated using bifurcation diagrams and Lyapunov exponent. A design methodology for building flexible and reconfigurable logic gate is outlined and the consequent enhancement in functionality space caused by the existence of three independent bifurcation parameters is demonstrated and compared with previous work.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126448757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Clipping Noise Mitigation by Adaptive Nulling and Nondata-Aided Compensation in Coded OFDM 编码OFDM中基于自适应零值和非数据辅助补偿的裁剪噪声抑制
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/DCAS51144.2020.9330646
N. Taherkhani, K. Kiasaleh
{"title":"Clipping Noise Mitigation by Adaptive Nulling and Nondata-Aided Compensation in Coded OFDM","authors":"N. Taherkhani, K. Kiasaleh","doi":"10.1109/DCAS51144.2020.9330646","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330646","url":null,"abstract":"Signal clipping is one of the simplest, yet effective method used to reduce the high peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) systems. However, clipping generates nonlinear distortion that causes spectral broadening and deteriorates the bit-error-rate (BER) performance of the OFDM system. This paper proposes a technique that incorporates Reed Solomon encoding and a feedback-based puncturing procedure to adaptively mitigate the clipping distortion on the OFDM spectrum and remove the out-of-band broadening caused by the intentional clipping. The new technique also employs a classical decision-aided method to iteratively compensate the residual frequency-domain distortion on data subcarriers. The simulation results show the effectiveness of the new technique in improving the BER of an OFDM system with various block sizes and practical clipping constraints.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128259981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Characterization and Assembly of an Efficient, Cost Effective Focused Ultrasound Transducer 高效、低成本聚焦超声换能器的表征与组装
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/DCAS51144.2020.9330669
Michael S. Maslakowski, S. Ilham, T. Hall, T. Subramanian, M. Kiani, M. Almekkawy
{"title":"The Characterization and Assembly of an Efficient, Cost Effective Focused Ultrasound Transducer","authors":"Michael S. Maslakowski, S. Ilham, T. Hall, T. Subramanian, M. Kiani, M. Almekkawy","doi":"10.1109/DCAS51144.2020.9330669","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330669","url":null,"abstract":"Ultrasonic imaging has been a staple of medical technology for the past 50 years. Focused ultrasound (FUS) is a rising new application of ultrasonic technologies that concentrates power at focal point(s). With the precision of the focal point, FUS offers a promise for a noninvasive yet highly conformal therapy option. This has encouraged a number of research groups to investigate its feasibility in different therapeutic applications. These applications include High Intensity Focused Ultrasound (HIFU) to coagulate cancerous tumors, Medium Intensity Focused Ultrasound (MIFU) to create a disruption in the Blood-Brain Barrier (BBB) for drug delivery or Low Intensity Focused Ultrasound (LIFU) for neuromodulation. The paper offers the procedures to assemble two cost effective options for piezoelectric FUS transducers. In addition, it characterizes their performance, the effects of bonding agents and the environments on them. This process was realized through both passive characterization of the reactants and active detection with a hydrophone.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127168427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
28 GHz Front –End with Duplexer in 40 nm CMOS Technology for 5G Beam-steering Transceivers 采用40纳米CMOS技术的28 GHz前端双工器，用于5G波束转向收发器
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/DCAS51144.2020.9453898
Panagiotis Gkoutis, Georgios Konidas, G. Kalivas
{"title":"28 GHz Front –End with Duplexer in 40 nm CMOS Technology for 5G Beam-steering Transceivers","authors":"Panagiotis Gkoutis, Georgios Konidas, G. Kalivas","doi":"10.1109/DCAS51144.2020.9453898","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9453898","url":null,"abstract":"This paper presents a (transceiver) TRX front-end structure design for Phased Array applications in 40nm CMOS Bulk process. The proposed structure consists of the Power Amplifier (PA) the Low Noise Amplifier (LNA) along with a monolithic transformer duplexer for Antenna connection applied in half-duplex systems. The front end covers the millimeter wave (MMW) 5G band. The PA design contains two differential cascode stages with capacitor neutralization technique achieving a small signal gain (S21) of 22.86dB with a -3dB bandwidth (BW) at 22-34 GHz. Moreover, the PA reaches a PAEmax of 31.66% and a Psat of 18.5 dBm. The LNA design consist of two cascode stages using current reuse technique at the first stage, obtaining 17.5 dB gain (S21) with a -3 dB bandwidth from 22.5 to 31 GHz. Both amplifiers are connected to the antenna through a compact duplexer with minimum losses and sufficient isolation.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122360558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low Power Fully Differential CMOS First Order All Pass Filter with 0.2- 4.8Hz Variable Pole Frequency 低功耗全差分CMOS一阶全通滤波器，0.2- 4.8Hz可变极点频率
2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS) Pub Date : 2020-11-15 DOI: 10.1109/DCAS51144.2020.9330645
Anindita Paul, J. Ramírez-Angulo, A. López-Martín, R. Carvajal, A. Díaz-Sánchez
{"title":"Low Power Fully Differential CMOS First Order All Pass Filter with 0.2- 4.8Hz Variable Pole Frequency","authors":"Anindita Paul, J. Ramírez-Angulo, A. López-Martín, R. Carvajal, A. Díaz-Sánchez","doi":"10.1109/DCAS51144.2020.9330645","DOIUrl":"https://doi.org/10.1109/DCAS51144.2020.9330645","url":null,"abstract":"A fully differential and fully integrated low voltage all pass filter operated in the sub-threshold region with variable pole frequency designed in CMOS 130nm technology is presented in this paper. It has only 0.09dB passband ripple. It works with ±200mV DC supplies and dissipates 0.7µW quiescent power. The Miller multiplication effect and quasi floating gate transistors make it possible to achieve a time constant in the range of seconds without consuming excessive Si area. The proposed filter's pole frequency can be varied from 242mHz to 4.8Hz by changing the Miller amplifier's gain. Simulation results in 130nm CMOS technology validate the proposed circuit.","PeriodicalId":428765,"journal":{"name":"2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122007112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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