Study on impact of process on Bitcell design in FinFets

Abstract

This paper discusses the impact of process scaling on bitcells in FinFets on 7nm and beyond. Every new process node is targeted to shrink the size of transistors. Shrinking in size makes the device vulnerable to process variations. The impact of the process variations creates new design challenges. Bitcells being at the forefront of every new process nodes face all-new levels of design complexity both in terms of the fabrication process and in designing. Bitcells are placed in every chip and the density of the same keeps growing. In the 7nm process, transistor density reaches approximately 96.5M Tr/mm2 with a bitcell dimension of 0.027um2. Moving towards 3nm, number of transistors could increase by 40%-50% for the same area, because of 2-fin minimum usage requirement. Having correct contingency circuits to fix failing bitcells is very important. The contingency circuits can be read assist, write assist circuits. As supply voltage is reduced, it is reaching towards the threshold voltage. Reduction in voltage to reduce the power only aggravates the problem. This requires an understanding of the impact of the process on bitcell qualifying parameters. This paper shows how the process is impacting the bitcells and its impact can be seen by measuring the bitcells qualifying parameters.