Proceedings of the 8th International Workshop on Network on Chip Architectures最新文献

Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip 具有成本效益的三维片上网络tsv共享拓扑设计

Proceedings of the 8th International Workshop on Network on Chip Architectures Pub Date : 2015-12-05 DOI: 10.1145/2835512.2835514

Poona Bahrebar, D. Stroobandt

引用次数: 0

Automated Power and Latency Management in Heterogeneous 3D NoCs 异构3D noc中的自动化电源和延迟管理

Proceedings of the 8th International Workshop on Network on Chip Architectures Pub Date : 2015-12-05 DOI: 10.1145/2835512.2835517

Awet Yemane Weldezion, M. Ebrahimi, M. Daneshtalab, H. Tenhunen

引用次数: 4

Rethinking Memory System Design (along with Interconnects) 重新思考内存系统设计(以及互连)

Proceedings of the 8th International Workshop on Network on Chip Architectures Pub Date : 2015-12-05 DOI: 10.1145/2835512.2835520

O. Mutlu

{"title":"Rethinking Memory System Design (along with Interconnects)","authors":"O. Mutlu","doi":"10.1145/2835512.2835520","DOIUrl":"https://doi.org/10.1145/2835512.2835520","url":null,"abstract":"The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck [27, 28]. At the same time, DRAM technology is experiencing difficult circuit and device scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more costly with conventional techniques (see, for example [7, 8, 11, 12, 15, 17, 18, 22, 23, 32]). In this talk, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we discuss three key solution directions: 1) enabling new memory architectures, functions, interfaces, and better integration of the memory and the rest of the system, including interconnects (e.g., [1, 2, 19, 20, 34-36]), 2) designing a memory system that intelligently employs multiple memory technologies and coordinates memory and storage management using non-volatile memory technologies (e.g., [16-18, 24, 25, 32, 33, 40-42]), 3) providing predictable performance and QoS to applications sharing the memory system (e.g., [3, 9, 10, 13, 14, 26, 29, 37-39]). As we discuss challenges and solution directions in memory, we will point out research opportunities in interconnects and memory-interconnect co-design (e.g., [2, 4-6, 19, 21, 30, 31]).","PeriodicalId":424680,"journal":{"name":"Proceedings of the 8th International Workshop on Network on Chip Architectures","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121234261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Task mapping and communication routing model for minimizing power consumption in multi-cores 多核环境下最小化功耗的任务映射和通信路由模型

Proceedings of the 8th International Workshop on Network on Chip Architectures Pub Date : 2015-12-05 DOI: 10.1145/2835512.2835515

Sergiu Carpov

引用次数: 3

Methodology to verify, debug and evaluate performances of NoC based interconnects 验证、调试和评估基于NoC互连性能的方法

Proceedings of the 8th International Workshop on Network on Chip Architectures Pub Date : 2015-12-05 DOI: 10.1145/2835512.2835521

Patrick Oury, N. Heaton, Stewart Penman

引用次数: 4

A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network 一种支持片上光网络服务质量的低延迟、高吞吐量多级仲裁方案

Proceedings of the 8th International Workshop on Network on Chip Architectures Pub Date : 2015-12-05 DOI: 10.1145/2835512.2835519

Jian Jie, Lai Mingche, Xiao Liquan

{"title":"A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network","authors":"Jian Jie, Lai Mingche, Xiao Liquan","doi":"10.1145/2835512.2835519","DOIUrl":"https://doi.org/10.1145/2835512.2835519","url":null,"abstract":"As a key technology in optical NoC design, the arbitration scheme should provide differential arbitration service with high throughput and low latency for various types and priorities of traffic in CMPs. In this work, we propose a fast hierarchical arbitration supporting Quality-of-Service. With a multi-priority data buffer queue, arbiters provide differential transmissions and guarantee service for all queues. Our arbiter also presents the transmit bound resource reservation scheme to reserve time slots for all nodes fairly. We propose fast arbitration with a layout of fast optical arbitration channels to decrease the arbitration period, thereby reducing packet transmitting delay. The simulation results show that with our hierarchical arbitration scheme, all nodes are allocated with almost equal service under various patterns; thus, the min-communication-bandwidth and max-transmit-delay is guaranteed to be 5% and 80 cycles under the overload demands. This scheme improves throughput by 17% compared to FeatherWeight under a self-similar traffic pattern and decreases arbitration delay by 15% to 2-pass arbitration.","PeriodicalId":424680,"journal":{"name":"Proceedings of the 8th International Workshop on Network on Chip Architectures","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115314870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

NoCVision: A Network-on-Chip Dynamic Visualization Solution 一种片上网络动态可视化解决方案

Proceedings of the 8th International Workshop on Network on Chip Architectures Pub Date : 2015-12-05 DOI: 10.1145/2835512.2835518

V. Gogte, Doowon Lee, Ritesh Parikh, V. Bertacco

引用次数: 0

System-Level Analysis of Network Interfaces for Hierarchical MPSoCs 分层mpsoc网络接口的系统级分析

Proceedings of the 8th International Workshop on Network on Chip Architectures Pub Date : 2015-12-05 DOI: 10.1145/2835512.2835513

J. Ax, Gregor Sievers, Martin Flasskamp, W. Kelly, T. Jungeblut, Mario Porrmann

引用次数: 7

Proceedings of the 8th International Workshop on Network on Chip Architectures 第八届芯片架构网络国际研讨会论文集

Proceedings of the 8th International Workshop on Network on Chip Architectures Pub Date : 1900-01-01 DOI: 10.1145/2835512

引用次数: 0