Methodology to verify, debug and evaluate performances of NoC based interconnects

Latest developments in electronic systems lead hardware architects to completely rethink the traffic exchanges inside Systems on Chip. Constraints on more parallelism, less power, more coherency, less order while designing system fabrics and interconnects infers a bunch of new design features. All of them need to be verified, all of them need to be evaluated with respect to their impact on system performance, power consumption and gate count. This paper discusses some of the most challenging features in NoCs and the way verification engineers and architects are tackling correctness and performance checking of them.