Automated Power and Latency Management in Heterogeneous 3D NoCs

Beside different core sizes in many-core Systems-on-Chip, the cost and reliability issues of TSVs move 3D NoCs toward heterogonous designs. Such heterogeneity introduces design complexity and new challenges for obtaining a high performance, low power, low area, and a reliable design. By taking all these factors into account, we propose a design as a combination of Q-Learning and deflection routing in a heterogeneous 3D NoCs. This design enables the routing algorithm to dynamically adjust itself to the underlying traffic condition and topology arrangement at run time. Thereby, the network can reach its optimal performance and minimum power consumption shortly after a reconfiguration either because of an occurred fault in the network or a traffic change.