5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era最新文献

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A behavioural study of nodes to conserve energy in wireless sensor networks 无线传感器网络中节点节能行为研究
Walid Charfi, M. Masmoudi, Walid Ferchichi, F. Derbel
{"title":"A behavioural study of nodes to conserve energy in wireless sensor networks","authors":"Walid Charfi, M. Masmoudi, Walid Ferchichi, F. Derbel","doi":"10.1109/DTIS.2010.5487583","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487583","url":null,"abstract":"This paper puts forward an optimization in routing processing for wireless sensor networks. The sensor node in such network is a battery-operated sensing device. These nodes are placed in space with a consideration to a base station that centralizes and consolidates the data transmitted or forwarded by sensor nodes. When optimizing the management of a Wireless Sensor Network, we have to take care of the consumption of energy that takes place while sensor nodes are running the routing process to send or relay a message to neighbors or to a Base Station. In this paper, we put forward a study of sensors' behavior by modeling and implementing a controller with Coloured Petri Network in order to ensure the reduction of energy consumption in some sensor networks in which each node can be activated or suspended as need be. The controller must deal with activation and suspension to apply a reconfiguring policy to nodes depending on an energy supply level in every sensor in order to obtain the lowest level possible of energy consumption and maintain the same service quality consisting in total coverage of the region to survey and the connection of active nodes to the functional network. The evaluation of our presented model is made by CPN-Tools.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123845658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electronic implementation of a speech processing system for auditory prosthesis 听觉假体语音处理系统的电子实现
B. Lamia, Ouni Kais, N. Ellouze
{"title":"Electronic implementation of a speech processing system for auditory prosthesis","authors":"B. Lamia, Ouni Kais, N. Ellouze","doi":"10.1109/DTIS.2010.5487593","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487593","url":null,"abstract":"In this paper we present the conception and the implementation of a speech processing interface for auditory prosthesis. This module is based on a numerical speech processing algorithm which modelizes the infected ear and generates the stimulus signals for the cilia cells. This interface uses a gammachirp filter bank (G.F.B) constituted of 16 band pass filters based on IIR filters. The excited electrodes and stimulus signals are selected after a spectral energy analysis of each band. The energy and the amplitude of the most significant impulse responses of the G.F.B outputs are quantized, coded and transmitted to the cochlea electrodes. To validate our work, we tested it on vowels, consonants then on several words pronounced by different speakers","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131358161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of RF PA nonlinearities based on cross-correlation between current and output voltage 基于电流和输出电压相互关的射频放大器非线性评估
P. Mota, J. M. da Silva, R. Veiga
{"title":"Evaluation of RF PA nonlinearities based on cross-correlation between current and output voltage","authors":"P. Mota, J. M. da Silva, R. Veiga","doi":"10.1109/DTIS.2010.5487560","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487560","url":null,"abstract":"The estimation of 1 dB compression and third-order intercept points can be obtained after the cross-correlation between dynamic current and output voltage of radio frequency power amplifiers. Estimation is performed using power measures and not power inferred from voltage measures. The underlining theory and a correlator that allows implementing this measurement on-chip are presented. The trade-off between measuring voltage or the actual power is also discussed. It is also shown that different information concerning the output load is obtained when observing the PA's output voltage and power. Simulation results, obtained with the model of a prototype demonstration chip show that good accuracy can be obtained with relatively simple measurement conditions. These results include the analysis of optimum stimuli amplitudes and the effect of noise in estimation accuracy.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128706782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A timing constraints control technique for embedded real time systems 嵌入式实时系统的时间约束控制技术
Mouna Ben Saïd, K. Loukil, N. Ben Amor, M. Abid, J. Diguet
{"title":"A timing constraints control technique for embedded real time systems","authors":"Mouna Ben Saïd, K. Loukil, N. Ben Amor, M. Abid, J. Diguet","doi":"10.1109/DTIS.2010.5487574","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487574","url":null,"abstract":"The real-time applications have a growing complexity and size which have to be well controlled. They can be viewed as a set of synchronized tasks, communicating and sharing critical resources. One of the main difficulties in the real-time application design is time constraints meeting. All tasks have to be running before their predefined deadlines. At this level, the integration of real time operating systems (RTOS) in the real-time systems design flow is necessary to enable scheduling tasks and managing the competition between them with respect of timing constraints. One of the problems encountered here is that one task may have different execution times. It may exceed its predefined WCET and then its deadline for many reasons. The problem is that one deadline exceeding may cause subsequent constraints violations which may disrupt the functioning of the system. This paper deals with this particular issue. It presents a new technique that permits the monitoring of tasks under execution. It controls their timing constraints by means of watchdog concept and detects deadline missing. That information is used to tune the target application parameters in order to satisfy timing constraints for the further computation iterations. We have implemented this technique in the RTOS MicroC/OS-II using the EDF scheduling policy. This technique has been validated using an Altera FPGA prototyping platform and the 3D rendering application.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127708947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Temperature and supply voltage aware power modeling of analog functions at system level 系统级模拟功能的温度和电源电压感知功率建模
A. Suissa, O. Romain, J. Denoulet, K. Hachicha, P. Garda
{"title":"Temperature and supply voltage aware power modeling of analog functions at system level","authors":"A. Suissa, O. Romain, J. Denoulet, K. Hachicha, P. Garda","doi":"10.1109/DTIS.2010.5487601","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487601","url":null,"abstract":"Nowadays a system level estimation method of power consumption for heterogeneous systems is a major concern. In this article, we introduce an empirical method for power consumption modeling of analog components at system level. The principal step of this method uses neural networks to approximate the mathematical curve of the power consumption as a function of the inputs, supply voltage and ambient temperature of an analog component. For an amplifier, we found an average error of 4.72% between our high level estimation and PSPICE power consumption results. This novel method is suitable for IP-based design and has three key features. Firstly, the method provides an online estimation of the instantaneous power consumption of analog blocks. Secondly, the method is generic as it can be applied to any analog component in any modeling and simulation environment. Thirdly, the method is suitable for the total (analog and digital) power consumption estimation of a heterogeneous system.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129060367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of the PSO technique to the Optimization of CMOS Operational Transconductance Amplifiers PSO技术在CMOS运算跨导放大器优化中的应用
S. Bennour, A. Sallem, M. Kotti, Emna Gaddour, M. Fakhfakh, M. Loulou
{"title":"Application of the PSO technique to the Optimization of CMOS Operational Transconductance Amplifiers","authors":"S. Bennour, A. Sallem, M. Kotti, Emna Gaddour, M. Fakhfakh, M. Loulou","doi":"10.1109/DTIS.2010.5487582","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487582","url":null,"abstract":"In this paper, we investigate the Optimizing Operational Transconductance Amplifiers through the constrained Particle Swarm Optimization (PSO). We optimize the folded cascode OTA performances, namely the static gain, the transition frequency, the common mode rejection ratio (CMRR) and the positive power-supply rejection ratio (PSRR). A comparaison with two other optimization methods shows good reached performances. The optimized circuit is used to design a 2nd order Biquad Gm-C low-pass filter.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134577462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 0.35 µm CMOS LC-tank injection-locked frequency divider 0.35µm CMOS LC-tank注入锁定分频器
Thaoura Chtioui, D. Ben Issa, A. Fakhfakh, M. Samet
{"title":"A 0.35 µm CMOS LC-tank injection-locked frequency divider","authors":"Thaoura Chtioui, D. Ben Issa, A. Fakhfakh, M. Samet","doi":"10.1109/DTIS.2010.5487603","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487603","url":null,"abstract":"A divide-by-2 injection-locked frequency divider (ILFD) has been designed in a 0.35 µm CMOS process. The ILFD circuit is realized with a differential CMOS LC-tank oscillator with an injection MOS. Simulation results show that at the supply voltage of 2.5 V and by tuning Vtune from 0 to 2.5 V, the tuning range of the free-running ILFD is from 1.84 to 2.89 GHz. At the injection signal power of 0 dBm, the locking range of the proposed ILFD is about 2.49 GHz from the incident frequency 3.53 to 6.02 GHz. The ILFD dissipate 3.43 mW. At the tuning voltage of 1.6 V the simulated phase noise of the free running ILFD is −125.6 dBc/Hz at 1.066 MHz offset frequency at 2.65 GHz and the phase noise of the locked output is −132.7 dBc/Hz while the phase noise of the injected signal is −126.7 dBc/Hz.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133392682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An MDE approach for modeling network on chip topologies 芯片拓扑网络建模的MDE方法
M. Elhaji, Pierre Boulet, S. Meftali, A. Zitouni, J. Dekeyser, R. Tourki
{"title":"An MDE approach for modeling network on chip topologies","authors":"M. Elhaji, Pierre Boulet, S. Meftali, A. Zitouni, J. Dekeyser, R. Tourki","doi":"10.1109/DTIS.2010.5487596","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487596","url":null,"abstract":"Network on Chip (NoC) is a research field path that primarily addresses the global communication in System on Chip (SoC).The selected topology of the components interconnects plays a prime role in the performance of NoC architecture, for NoC conception, high-level synthesis approaches are utilized thus the behaviorally description of the system is refined into an accurate register-transfer-level (RTL) design for SoC implementation. In the recent MARTE (Modeling and Analysis of Real-time and Embedded Systems) Profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topology. This paper presents a contribution for a new methodology for modeling NoC based Model Driven Architecture and the Modeling and Analysis of Real-Time and embedded System (MARTE), it aims to prove the effectiveness of standard MARTE in modeling irregular or globally irregular locally regular architectures. We will start this work by high level abstraction to reach low level through generated VHDL code.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123898056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CIG: A CAD tool for IP integration in SoC design 在SoC设计中集成IP的CAD工具
F. Abbes, N. Benamor, M. Abid, Amira Yanguy
{"title":"CIG: A CAD tool for IP integration in SoC design","authors":"F. Abbes, N. Benamor, M. Abid, Amira Yanguy","doi":"10.1109/DTIS.2010.5487577","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487577","url":null,"abstract":"Actually, SoC design is based on the reuse of Intellectual Property (IP). Designer's attempts such as flexibility, cost constraints, high performance and time to market can thus be helpfully managed. However, the correct integration of the generated architectures/components in a design implies complex verification and design problems. Since IPs are heterogeneous, the design of communication interfaces between them is more and more difficult. In this paper, we present a CIG: Communication Interface Generator; a CAD tool automating the integration process of hardware accelerators/ coprocessors aiming data flow emerged systems.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125358085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Delay Locked Loop for fine time base generation in a positron emission tomography scanner 一种用于正电子发射断层扫描仪中精细时基生成的延时锁环
M. Abidi, K. K. Calliste, M. Kanoun, S. Panier, L. Arpin, M. Tetraul, J. Pratte, R. Fontaine
{"title":"A Delay Locked Loop for fine time base generation in a positron emission tomography scanner","authors":"M. Abidi, K. K. Calliste, M. Kanoun, S. Panier, L. Arpin, M. Tetraul, J. Pratte, R. Fontaine","doi":"10.1109/DTIS.2010.5487578","DOIUrl":"https://doi.org/10.1109/DTIS.2010.5487578","url":null,"abstract":"In this paper, an analog Delay Locked Loop with fixed latency of one clock cycle is proposed. It was implemented with differential delay cells in order to reduce noise, and based on a precise dynamic phase comparator. With a 1.8 V supply and a 100 MHz input clock, the DLL consumes 3.4 mW and the measured jitter is 3.9 ps rms. It was implemented on a 0.18 μm TSMC CMOS technology and occupies an active area of 0.0022 mm2.","PeriodicalId":423978,"journal":{"name":"5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121949706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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