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2006 IEEE International Symposium on Circuits and Systems最新文献

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A semiblind receiver for space-time block-coded downlink multirate DS-CDMA systems 时空分组编码下行多速率DS-CDMA系统的半盲接收机
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692607
S. Phrompichai, P. Yuvapoositanon
{"title":"A semiblind receiver for space-time block-coded downlink multirate DS-CDMA systems","authors":"S. Phrompichai, P. Yuvapoositanon","doi":"10.1109/ISCAS.2006.1692607","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692607","url":null,"abstract":"In this paper, a novel space-time block-coded (STBC) semiblind receiver for wideband code division multiple access (WCDMA) downlink multirate is proposed. The receiver exploits distinct advantages of training based and blind update algorithms by means of an adaptive mixing parameter. The training is updated using continually transmitted pilot code sequence as the training signal whereas the blind part uses the decision directed estimate. Unlike the existing pilot-based receivers, the proposed receiver employs a multiple constraint to give the exact solution for detection of the desired user. Moreover, the proposed receiver needs reduced transmitted power and lower computation complexity than the space-time chip receivers","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125266783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications 一个低功耗的1.056 GS/s分辨率可切换的5位/6位闪存ADC，用于超宽带应用
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693581
Junxia Ma, Sai-Weng Sin, U. Seng-Pan, R. Martins
{"title":"A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications","authors":"Junxia Ma, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/ISCAS.2006.1693581","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693581","url":null,"abstract":"A 1.056 GS/s, 5-bit/6-bit switchable flash analog-to-digital converter (ADC) is designed in 0.18-mum CMOS, which is suitable to be used in an OFDM-UWB transceiver. A resolution switchable structure is proposed to optimize power consumption according to the dynamic requirement of the application. Two-stage interpolation and averaging techniques are employed to average the offset of the preamplifiers. Monte Carlo simulation results show that the proposed ADC achieves 4.2b/5.0b ENOB in 5-bit/6-bit working modes with a 413-MHz input signal. The mean value of DNL and INL is 0.32 and 0.56 LSB for 5-bit mode, while 0.47 and 0.62 LSB for 6-bit mode. The analog part consumes 36 mW and 98 mW from a 1.8-V supply in 5-bit and 6-bit operation mode, respectively","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125332049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
MM11 based flash memory cell model including characterization procedure 基于MM11的闪存单元模型，包括表征过程
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693385
B. Saillet, A. Régnier, J. Portal, B. Delsuc, R. Laffont, P. Masson, R. Bouchakour
{"title":"MM11 based flash memory cell model including characterization procedure","authors":"B. Saillet, A. Régnier, J. Portal, B. Delsuc, R. Laffont, P. Masson, R. Bouchakour","doi":"10.1109/ISCAS.2006.1693385","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693385","url":null,"abstract":"The objective of this paper is to present a flash cell model for static and transient simulations. As a core element of this model, a Philips MOS model (MM11) model has been used coupled with the charge neutrality expression in the structure. The charge neutrality, including the charge trapped in the floating gate, is applied to determine the potential of the floating gate. From the floating gate potential, related to the terminal voltages, the drain current and the different charges present in the cell structure are calculated with the MM11 formulation. This pragmatic model takes into account the different injection mechanism (CHE, CHISEL and FN). Moreover, the characterization procedure developed under ICCAP to extract the MM11 model card as well as the tunnel current parameters is presented. This model has been successfully implemented in ELDO","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125334555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A/D and D/A converters by spike-interval modulation of simple spiking neurons 简单尖峰神经元的尖峰间隔调制的A/D和D/A转换器
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693284
Aya Tanaka, H. Torikai, Toshimichi Saito
{"title":"A/D and D/A converters by spike-interval modulation of simple spiking neurons","authors":"Aya Tanaka, H. Torikai, Toshimichi Saito","doi":"10.1109/ISCAS.2006.1693284","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693284","url":null,"abstract":"This paper studies A/D and D/A converters based on spiking neurons. The neurons repeat integrate-and-fire behavior between threshold and base signals and can output a variety of spike-trains. For the A/D conversion, an analog dc input is applied as an initial value and the spike-train is transformed into a digital output via spike-interval modulation. For the D/A conversion, a digital input is applied to switch base level and an analog output is given as phase of final spike within a given time limit. We then present a reconfigurable circuit that can realize both A/D and D/A converters by changing shape of base and threshold waveforms. The circuit operation is confirmed by PSPICE simulation","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125382608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fixed-point configurable hardware components for adaptive filters 用于自适应滤波器的定点可配置硬件组件
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693331
R. Rocher, N. Hervé, D. Ménard, O. Sentieys
{"title":"Fixed-point configurable hardware components for adaptive filters","authors":"R. Rocher, N. Hervé, D. Ménard, O. Sentieys","doi":"10.1109/ISCAS.2006.1693331","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693331","url":null,"abstract":"To reduce the gap between the VLSI technology capability and the designer productivity, design reuse based on IP (intellectual properties) is commonly used. In terms of arithmetic accuracy, the generated architecture can generally only be configured through the input and output word-lengths. In this paper, a new kind of fixed-point arithmetic IP is presented through the LMS and delayed-LMS examples. The operator and memory word-lengths are optimized under an accuracy constraint defined by the user. To significantly reduce the optimization and design times, the architecture parameter determination is based on analytical approach","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125399650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory 一种在内容可寻址存储器中实现高效单周期范围匹配的混合编码方案
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692704
Ying Yu, R. Hoare, A. Jones, Ralph Sprang
{"title":"A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory","authors":"Ying Yu, R. Hoare, A. Jones, Ralph Sprang","doi":"10.1109/ISCAS.2006.1692704","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692704","url":null,"abstract":"Content addressable memory (CAM) is a parallel search engine chip that has been proven to accelerate network appliance functions that are search-intensive by nature, such as routing table lookups. CAMs enable searching for a match of a single input with hundreds of thousands of entries in parallel in a single clock cycle. However, CAMs are inefficient in matching a numeric range with existing encoding methods. Two-hot, binary and Gray encodings exhibit a depth scalability problem where the CAM depth required increases with the maximum number M in the range. One-hot and Johnson encodings exhibit poor CAM width scalability O(M). We present a unique hybrid encoding scheme mixing the features of two-hot and Johnson codes to solve both scalability problems. For an arbitrary range, it uses only three CAM entries in depth regardless of M, and has a width scaling of O(radicM ). Therefore, this hybrid encoding scheme can be efficiently applied to CAM-based range matching with arbitrary ranges, while maintaining single cycle searching","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126601338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optical sensor integrated CNN for real-time computational applications 光学传感器集成CNN用于实时计算应用
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693439
K. Karahaliloglu, Patrick Gans, N. Schemm, S. Balkır
{"title":"Optical sensor integrated CNN for real-time computational applications","authors":"K. Karahaliloglu, Patrick Gans, N. Schemm, S. Balkır","doi":"10.1109/ISCAS.2006.1693439","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693439","url":null,"abstract":"A previously implemented CNN layer based on a bio-inspired system model is integrated with optical sensors comprised of PN type photodiodes and the design is fabricated in CMOS technology. The implemented test chip is measured and obtained results are presented. The sensor integration marks a new step in prototyping of this system in CMOS, which allows the cell states to be programmed via light interactions, rather than successive state programming procedure which was utilized previously. It is shown that the cell input states in the network can be successfully introduced via exposure of the 2D array to a light source. The followed custom design methods and this remarkably compatible sensor integration can lead to compact on-chip solutions for real-time high performance applications, including but not limited to certain types of image processing","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126708003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A universal common-source and common-drain model for 1-20GHz frequency range 1-20GHz频率范围的通用共源共漏模型
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693334
S. Sridharan, S. Bandi, C. Washburn, P. R. Mukund, J. Kolnik, K. Paradis, S. Howard, J. Burleson
{"title":"A universal common-source and common-drain model for 1-20GHz frequency range","authors":"S. Sridharan, S. Bandi, C. Washburn, P. R. Mukund, J. Kolnik, K. Paradis, S. Howard, J. Burleson","doi":"10.1109/ISCAS.2006.1693334","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693334","url":null,"abstract":"Extraction plays an important role in the performance of device models especially in the high frequency regime. The present day extraction techniques mostly use a grounded source or common source (CS) device configuration. The models extracted from the grounded source devices are then used for devices in other configurations in a circuit application. This leads to discrepancies in accurate prediction of the circuit performance. This work investigates, the applicability of the models extracted using CS for other device configurations. It was shown with the help of measured data, in the frequency range of 1-20 GHz, that the models extracted from CS configuration do not predict the performance of a device in common drain (CD) configuration. Based on the above observation, a universal gate impedance model that works for both CS and CD configurations for BSIM3v3 was developed. The gate impedance model was then extended to BSIM4 for both CS and CD configurations. The models for BSIM3v3 and BSIM4 are verified using simulations and compared with the measured data","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115042361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An improved design approach for LC tank VCOs LC储罐vco的改进设计方法
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693787
M. Prochaska, K. Bohle, W. Mathis
{"title":"An improved design approach for LC tank VCOs","authors":"M. Prochaska, K. Bohle, W. Mathis","doi":"10.1109/ISCAS.2006.1693787","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693787","url":null,"abstract":"Fully integrated LC tank oscillators are widely used because they are able to fulfil the increasing requirements in the field of RF applications. In this paper formulas for investigations of the stability as well as the amplitude of CMOS LC tank oscillators are derived, where an overall model of nonlinear gain elements is used. By means of these results we are able to present an improved design approach which gives a deeper insight into the functionality of LC tank VCOs","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115110205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An adaptive search algorithm based on block classification for fast block motion estimation 基于块分类的自适应搜索算法用于快速块运动估计
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693501
Meng-chou Chang, Jung-shan Chien
{"title":"An adaptive search algorithm based on block classification for fast block motion estimation","authors":"Meng-chou Chang, Jung-shan Chien","doi":"10.1109/ISCAS.2006.1693501","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693501","url":null,"abstract":"This paper presents a new motion estimation algorithm, called the adaptive motion estimation (AME). The AME algorithm exploits the information gathered from the previous frame to derive a parameter, called CF (correlation parameter), and employs CF to classify the blocks in the current frame into potentially dependent blocks and potentially independent blocks. AME applies different motion estimation methods for potentially dependent blocks and potentially independent blocks to achieve better estimation accuracy and lower computational complexity. Simulation results showed that the proposed AME algorithm has both lower computational complexity and higher PSNR than other motion estimation algorithms, such as three-step search (TSS), new three-step search (NTSS), four-step search (4SS), and the NPSA (new predictive search area) algorithm","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115172672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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