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2006 IEEE International Symposium on Circuits and Systems最新文献

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A closed form solution to L/sub 2/-sensitivity minimization of second-order state-space digital filters 二阶状态空间数字滤波器L/sub /灵敏度最小化的封闭解
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2008-05-01 DOI: 10.1093/ietfec/e91-a.5.1268
Shunsuke Yamaki, M. Abe, M. Kawamata
{"title":"A closed form solution to L/sub 2/-sensitivity minimization of second-order state-space digital filters","authors":"Shunsuke Yamaki, M. Abe, M. Kawamata","doi":"10.1093/ietfec/e91-a.5.1268","DOIUrl":"https://doi.org/10.1093/ietfec/e91-a.5.1268","url":null,"abstract":"This paper proposes a closed form solution to L2-sensitivity minimization of second-order state-space digital filters. Restricting ourselves to the 2nd order case of state-space digital filters, we can formulate L2-sensitivity minimization problem by hyperbolic functions. As a result, L2-sensitivity minimization problem can be converted into a problem to find the solution to a 4th degree polynomial equation of constant coefficients, which can be algebraically solved in closed form without iterative calculations","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124874941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Low-voltage CMOS syllabic-companding log domain filter 低压CMOS音节压缩对数域滤波器
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2007-05-27 DOI: 10.1109/ISCAS.2007.378729
I. Akita, K. Wada, Y. Tadokoro
{"title":"Low-voltage CMOS syllabic-companding log domain filter","authors":"I. Akita, K. Wada, Y. Tadokoro","doi":"10.1109/ISCAS.2007.378729","DOIUrl":"https://doi.org/10.1109/ISCAS.2007.378729","url":null,"abstract":"This paper presents a low-voltage CMOS syllabic-companding log domain filter with wide dynamic range. The proposed filter is synthesized based on the idea of varying a voltage which is fixed on a dynamically adjustable biasing (DAB) filter. A low-voltage envelope detector necessary for a DAB filter is also designed including quantization mechanism. Simulation results show the proposed filter is effective in widening dynamic range","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134369476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new current-mode incremental signaling scheme with applications to Gb/s parallel links 一种适用于Gb/s并行链路的新型电流模式增量信令方案
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2007-02-12 DOI: 10.1109/TCSI.2006.885977
Tao Wang, F. Yuan
{"title":"A new current-mode incremental signaling scheme with applications to Gb/s parallel links","authors":"Tao Wang, F. Yuan","doi":"10.1109/TCSI.2006.885977","DOIUrl":"https://doi.org/10.1109/TCSI.2006.885977","url":null,"abstract":"A new current-mode incremental signaling scheme for high-speed parallel links is proposed. The signaling scheme requires only N+1 physical paths for N parallel bits. It possesses the intrinsic advantages of current-mode signaling including high data rates, large signal swing, low switching noise injection, and superior signal integrity. The current-integrating front-end offers the key advantages of a low and tunable input impedance for channel termination, large bandwidth, and effective suppression of high-frequency noise coupled to the channels. Simulation results of a 4-bit parallel link implemented in a 0.13 mum, 1.2V CMOS technology demonstrate that the proposed signaling scheme is capable of transmitting parallel data at 10 Gbps","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125528398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Robustness optimization of parametric speech watermarking 参数化语音水印的鲁棒性优化
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-09-11 DOI: 10.1109/ISCAS.2006.1692575
A. Gurijala, J. Deller, D. Joachim
{"title":"Robustness optimization of parametric speech watermarking","authors":"A. Gurijala, J. Deller, D. Joachim","doi":"10.1109/ISCAS.2006.1692575","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692575","url":null,"abstract":"Parameter-embedded watermarking is effected through slight perturbations of parametric models of some deeply-integrated dynamics of the speech signal. In set-membership filtering (SMF) based parametric watermarking, linear predictor (LP) coefficients of the original speech are modified subject to an objective fidelity constraint. SMF is used to obtain sets of allowable parameter perturbations (i.e., watermarks) subject to a constraint on the error between the watermarked and original material. This paper discusses the robustness of SMF based watermarking to filtering, quantization and combination attacks. An important consideration in watermark robustness is the energy of the watermark signal (difference between watermarked and original signals). The most robust watermark is obtained from perturbed LP coefficients at the boundary of the membership set. A constrained optimization problem is solved to obtain the best watermarks for filtering and quantization attacks","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115112966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel concept for stateless random bit generators in cryptographic applications 密码学应用中无状态随机位生成器的新概念
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-09-11 DOI: 10.1109/ISCAS.2006.1692586
M. Bucci, L. Giancane, R. Luzzi, M. Varanonuovo, A. Trifiletti
{"title":"A novel concept for stateless random bit generators in cryptographic applications","authors":"M. Bucci, L. Giancane, R. Luzzi, M. Varanonuovo, A. Trifiletti","doi":"10.1109/ISCAS.2006.1692586","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692586","url":null,"abstract":"A new, patent pending, concept for a random bit generator, suitable to be integrated in a cryptographic device, is presented. The proposed circuit exploits the relative jitter between two identical ring oscillators sharing the same delay elements and shows several advantages with respect to other oscillator-based generators reported in the technical literature. In particular, the generator is stateless and therefore easily testable accordingly to what is reported in (Bucci, 2005). Moreover, the generation throughput is automatically adapted to the available noise in the circuit thus guaranteeing the statistical quality (minimum entropy) of the generated bits. To validate the proposed circuit, simulation results on a 0.12mum CMOS process are reported","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127282763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A new watermarking system for joint ownership verification 一种新的共同所有权验证水印系统
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-09-11 DOI: 10.1109/ISCAS.2006.1693943
Guofu Gui, Ling-ge Jiang, Chen He
{"title":"A new watermarking system for joint ownership verification","authors":"Guofu Gui, Ling-ge Jiang, Chen He","doi":"10.1109/ISCAS.2006.1693943","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693943","url":null,"abstract":"Few watermarking systems are designed to resolve the problem of joint ownership verification. This paper proposes a new watermarking system for proving joint ownership of digital images, where a TTP is needed. The watermarking key is shared by all co-owners using Shamir's secret sharing scheme as presented by Shamir (1979). Furthermore, each owner is distributed a detection watermark for individual verification. The simulation results demonstrate that the proposed system is effective, and it can resist malicious attacks performed by the co-owners and some common image processing operations","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121543941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A tunable 0.5-1.3 GHz CMOS 2nd order bandpass filter with 50/spl Omega/ input-output impedance matching 具有50/spl ω /输入输出阻抗匹配的可调谐0.5-1.3 GHz CMOS二阶带通滤波器
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692722
V. Stornelli, G. Ferri, G. Leuzzi, A. Marcellis
{"title":"A tunable 0.5-1.3 GHz CMOS 2nd order bandpass filter with 50/spl Omega/ input-output impedance matching","authors":"V. Stornelli, G. Ferri, G. Leuzzi, A. Marcellis","doi":"10.1109/ISCAS.2006.1692722","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692722","url":null,"abstract":"In this paper, a high Q tunable 2nd order band-pass filter, working in the RF frequency range and designed in a standard AMS 0.35mum CMOS technology, is proposed. The filter is based on three different stages that perform the input and output impedance matching, the bandpass function and prevent instabilities; therefore, it is suitable for integrated front-end RF applications. Simulation results have shown a tunable range between 500 MHz and 1.3 GHz with good input and output impedance matching and a low noise figure. Moreover, this circuit presents a compression-point level higher than -22dBm and a quality factor Q higher than 60","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115155941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Analog circuit synthesis: a search for the Holy Grail? 模拟电路合成:寻找圣杯?
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692872
S. Huss
{"title":"Analog circuit synthesis: a search for the Holy Grail?","authors":"S. Huss","doi":"10.1109/ISCAS.2006.1692872","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692872","url":null,"abstract":"Hardware design is a process of refining an idea from a highly abstract form to a concrete, physical implementation. Along the way, a design is continually transformed from a given state of abstraction to another less abstract representation, finally ending with physical design. Such transformations are achieved through synthesis - a standard method in digital design. Analog circuits, however, are still designed in practice in a bottom-up, manual style. This paper summarises the results of past research in analog synthesis and outlines a refinement-centric methodology for analog circuit synthesis","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115472480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Taylor-series technique for moving source localization in the presence of sensor location errors 存在传感器定位误差时的运动源定位泰勒级数技术
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692775
Xiaoning Lu, K. C. Ho
{"title":"Taylor-series technique for moving source localization in the presence of sensor location errors","authors":"Xiaoning Lu, K. C. Ho","doi":"10.1109/ISCAS.2006.1692775","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692775","url":null,"abstract":"Uncertainty in sensor (receiver) locations can seriously deteriorate the source localization accuracy. A localization algorithm needs to take the sensor location errors into account in order to improve source location estimate. This paper considers the localization for the position and velocity of a moving source using the time differences of arrival (TDOAs) and frequency differences of arrival (FDOAs) of a signal received at a number of sensors that have random location errors. The proposed method is based on the Taylor-series method that jointly estimates both the source and sensor locations simultaneously. Simulation results show that with a reasonable initial guess close to the true solution to begin with, the proposed method converges to the true solution and achieves the CRLB accuracy for both near-field and far-field sources","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115637482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A binary-to-thermometer decoder with built-in redundancy for improved DAC yield 内置冗余的二进制到温度计解码器，可提高DAC产量
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692860
G. Radulov, P. Quinn, Pieter C. W. van Beek, H. Hegt, A. Roermund
{"title":"A binary-to-thermometer decoder with built-in redundancy for improved DAC yield","authors":"G. Radulov, P. Quinn, Pieter C. W. van Beek, H. Hegt, A. Roermund","doi":"10.1109/ISCAS.2006.1692860","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692860","url":null,"abstract":"This paper describes an architecture for binary-to-thermometer decoders used in segmented D/A converters. To improve basic converter characteristics, the architecture features redundant output thermometer code. The main concept offers two modes of operation. Each mode generates a different thermometer output, i.e. a different switching sequence for the DAC MSB thermometer analog elements. This results in two different transfer characteristics of the whole DAC for the same mismatch errors of its elements. After on-chip or off-chip measurements, the more linear transfer characteristic can be selected. In this way, chip yield is improved and the design requirements can be relaxed. Ultimately, the advantages introduced by the proposed decoder lead to cheaper and smaller D/A converters","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115725114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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