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2006 IEEE International Symposium on Circuits and Systems最新文献

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Design and implementation of multi-directional grid multi-torus chaotic attractors 多向网格多环混沌吸引子的设计与实现
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692685
Simin Yu, Jinhu Lu
{"title":"Design and implementation of multi-directional grid multi-torus chaotic attractors","authors":"Simin Yu, Jinhu Lu","doi":"10.1109/ISCAS.2006.1692685","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692685","url":null,"abstract":"This paper introduces a novel four-order system, which can generate one-directional (1-D) n-torus, two-directional (2-D) n times m-torus, three-directional (3-D) n times m times l-torus, four-directional (4-D) n times m times l times p-torus chaotic attractors. Furthermore, a novel block circuit diagram is designed for the hardware implementation of multi-directional grid multi-torus chaotic attractors. This is the first time in the literature to experimentally verify a 5 times 5 times 3 times 3-torus chaotic attractors","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115221094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Short periodic orbits and topological entropy for the Chua's circuit 蔡氏电路的短周期轨道和拓扑熵
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692923
Z. Galias
{"title":"Short periodic orbits and topological entropy for the Chua's circuit","authors":"Z. Galias","doi":"10.1109/ISCAS.2006.1692923","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692923","url":null,"abstract":"In this work, an analysis of Chua's circuit in terms of short periodic orbits is carried out. The circuit is considered with two sets of parameter values, for which the Roessler-type and the double-scroll attractors are observed. Using the number of short periodic orbits and their periods, we find estimates for the topological entropy of the Poincare map and the flow","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115984293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A frequency domain based TEQ design for DSL systems 基于频域的DSL系统TEQ设计
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692900
Yuan-Pei Lin, Yu-Pin Lin, See-May Phoong
{"title":"A frequency domain based TEQ design for DSL systems","authors":"Yuan-Pei Lin, Yu-Pin Lin, See-May Phoong","doi":"10.1109/ISCAS.2006.1692900","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692900","url":null,"abstract":"In this paper, we propose a frequency domain based design method for designing TEQ (time domain equalizer) for DSL (digital subscriber loops) applications. In DSL applications, usually frequency division multiplexing is used to separate the upstream and downstream signals. In either direction of transmission, some of the frequency bands are not used for transmission. Interference is formulated and minimized in the frequency domain to take advantage of the unused frequency bands. The frequency domain approach allows us to have a more direct control over the frequency response of the resulting TEQ, which is crucial in the final achievable transmission bit rates. The simulation examples demonstrate that the proposed method shortens the channel effectively and very good transmission bit rates can be achieved","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"349 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116002946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications 7.5mW, 11位连续时间σ - δ A/D转换器，用于WLAN应用
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693609
R. Schoofs, M. Steyaert, W. Sansen
{"title":"A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications","authors":"R. Schoofs, M. Steyaert, W. Sansen","doi":"10.1109/ISCAS.2006.1693609","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693609","url":null,"abstract":"A third-order continuous-time DeltaSigma analog-to-digital converter is designed for the conversion of an input signal bandwidth of 10MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed, low-power building blocks of the modulator. The presented converter achieves a dynamic range of 72dB and a signal-to-noise-and-distortion-ratio of 66dB. The modulator consumes 7.5mW. It is integrated in a 0.18mum standard CMOS technology and occupies an area of 1.65mm2","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"498 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116194320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator 一种新型有效带通半mash σ - δ调制器，具有双采样无失配谐振腔
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692652
Chon-In Lao, U. Seng-Pan, R. Martins
{"title":"A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator","authors":"Chon-In Lao, U. Seng-Pan, R. Martins","doi":"10.1109/ISCAS.2006.1692652","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692652","url":null,"abstract":"This paper presents a novel high-order bandpass semi-MASH sigma-delta modulator (4-2+2-...-2+2mb) with fs/4 center frequency. The proposed topology employs a semi-MASH technique with a 4-2Lmb topology to achieve an expandable and extendable high-order bandpass noise-shaping. To illustrate the architecture's behavior an 8xOSR 12-order 1.5-bit semi-MASH sigma-delta modulator is designed achieving 88 dB SNQR (signal-to-quantization-error ratio) at -1dB overloading point (90% of the modulator full-scale). A double-sampling mismatch-free single-opamp double-delay resonator is also proposed for the semi-MASH sub-stages to improve the overall design performance","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116417451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Binary LNS-based naive Bayes hardware classifier for spam control 垃圾邮件控制的基于二进制lns的朴素贝叶斯硬件分类器
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693424
M. N. Marsono, M. El-Kharashi, F. Gebali
{"title":"Binary LNS-based naive Bayes hardware classifier for spam control","authors":"M. N. Marsono, M. El-Kharashi, F. Gebali","doi":"10.1109/ISCAS.2006.1693424","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693424","url":null,"abstract":"We propose a hardware architecture for a naive Bayes classifier in the context of e-mail classification for spam control. Our proposal presents a word-serial naive Bayes classifier architecture that utilizes the logarithmic number system (LNS) to reduce the computational complexity. We present the hardware architecture for non-iterative binary LNS recoding using a look-up table approach. Our design was synthesized targeting an Altera Stratix CPLD device. The synthesized classifier was functionally verified with a MATLAB implementation. Our binary LNS naive Bayes classifier exhibits high e-mail classification throughput of more than 30 thousands e-mails per second","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116530292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Estimation of the weighted maximum switching activity in combinational CMOS circuits 组合CMOS电路中加权最大开关活度的估计
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693238
F. Aloul, A. Sagahyroon
{"title":"Estimation of the weighted maximum switching activity in combinational CMOS circuits","authors":"F. Aloul, A. Sagahyroon","doi":"10.1109/ISCAS.2006.1693238","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693238","url":null,"abstract":"To achieve high reliability in VLSI designs, estimation of the maximum power dissipation during the design cycle is becoming important. In previous work, it was shown that maximizing dissipation is equivalent to maximizing gate output activity, appropriately weighted to account for differing load capacitances. Recent advances in Boolean satisfiability (SAT) models and algorithms have made it tempting to use satisfiability-based techniques in solving various VLSI design-related problems such as verification and test generation. SAT solvers have also been extended to handle 0-1 integer linear programming (ILP) problems. In this paper, we present an ILP-based solution to compute the maximum weighted activity of combinational circuits. The problem is formulated as an ILP instance and the new SAT-based ILP solvers are used to find an estimate for the power dissipation. For performance comparison, the problem is also solved using generic ILP solvers. The validity of the proposed approach is demonstrated using benchmarks from the MCNC suite","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122917721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Improved reversible integer transform 改进可逆整数变换
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692779
S. Pei, Jian-Jiun Ding
{"title":"Improved reversible integer transform","authors":"S. Pei, Jian-Jiun Ding","doi":"10.1109/ISCAS.2006.1692779","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692779","url":null,"abstract":"Integer transform are the discrete transforms whose entries are summations of 2-k. If for an integer transform, we can perfectly recover the input from the output, we call it the reversible integer transform. In 2001, Hao and Shi developed an algorithm that can convert any reversible non-integer transform into a reversible integer transform. In this paper, we improve their works. First, we simplify the way of derivation. Then, we analyze the approximation error and introduce the way to reduce it. We also discuss the problem of bit constraint and how to reduce the number of time cycle in implementation","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122466501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Novel linearization technique for low-distortion high-swing CMOS switches with improved reliability 新颖的低失真高摆幅CMOS开关线性化技术，提高了开关的可靠性
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693006
A. Galhardo, J. Goes, N. Paulino
{"title":"Novel linearization technique for low-distortion high-swing CMOS switches with improved reliability","authors":"A. Galhardo, J. Goes, N. Paulino","doi":"10.1109/ISCAS.2006.1693006","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693006","url":null,"abstract":"This paper proposes a linearization technique for low-distortion high-swing CMOS switches based on a new method of improving the linearity of the NMOS and PMOS conductances. This method has the advantage over conventional clock-boosting techniques of avoiding large gate voltages thus reducing the stress on the gate capacitance. Simulated results of a practical sample-and-hold circuit show that, using this technique, linearity levels compatible with 12-b can be reached over the Nyquist band","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122519046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Block precoder-based energy constrained DFE 基于块预编码器的能量约束DFE
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693020
R. Merched, I. S. G. Figueiredo
{"title":"Block precoder-based energy constrained DFE","authors":"R. Merched, I. S. G. Figueiredo","doi":"10.1109/ISCAS.2006.1693020","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693020","url":null,"abstract":"Decision feedback equalizers (DFE) employing energy constraints have been successfully used to limit the feedback of wrong decisions that lead to the well known error propagation phenomenon. This paper extends the energy constraint formulation proposed for the scalar DFE, to the class of block memoryless DFE structures that employ zero-padding transmission redundancy. We further show how to make use of fast order recursive relations in order to obtain the filters efficiently. Computer simulations verify the improved BER performance of the proposed scheme over its unconstrained block DFE counterpart","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122558618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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