发布求助
文献互助 智能选刊 最新文献

2006 IEEE International Symposium on Circuits and Systems最新文献

筛选
英文 中文
A statistical approach to localize passive RFIDs 一种定位无源rfid的统计方法
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692717
C. Alippi, D. Cogliati, Giovanni Vanini
{"title":"A statistical approach to localize passive RFIDs","authors":"C. Alippi, D. Cogliati, Giovanni Vanini","doi":"10.1109/ISCAS.2006.1692717","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692717","url":null,"abstract":"We suggest a novel method for localizing passive radio frequency identification (RFID) tags based on a Bayesian approach. The localization framework requires a suitable number of tag-readers deployed in the area under investigation and connected to antennas which, provided with rotation ability, perform the detection task by scanning each angular sector at different power levels. Since readers are programmed to detect tags at increasing transmitting power (and provide binary tag/no tag information), we take advantage of the reader interrogation results to develop a Bayesian model for tags localization. By testing the solution with off-the-shelf UHF tags were experimented the accuracy of the method that, in a 5mtimes4m environment, provides an average error in localization of about 0.6 meters. This without exploiting any a priori information of the location, orientation or the power delivered to the tag (since not available in actual tags) which would significantly improve localization accuracy","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127536136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs 基于门控振荡器的cdr抖动和频率容差分析与建模
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693033
A. Tajalli, P. Muller, S. M. Atarodi, Y. Leblebici
{"title":"Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs","authors":"A. Tajalli, P. Muller, S. M. Atarodi, Y. Leblebici","doi":"10.1109/ISCAS.2006.1693033","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693033","url":null,"abstract":"This paper presents an approach to analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition to their acceptable FTOL and flexible topology, have made them very suitable for short-haul multi-rate applications","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124769503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Stability analysis of higher-order delta-sigma modulators using the describing function method 用描述函数法分析高阶δ - σ调制器的稳定性
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692655
J. Lota, M. Al-Janabi, I. Kale
{"title":"Stability analysis of higher-order delta-sigma modulators using the describing function method","authors":"J. Lota, M. Al-Janabi, I. Kale","doi":"10.1109/ISCAS.2006.1692655","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692655","url":null,"abstract":"The aim of this paper is to determine the stability of higher-order Delta-Sigma modulators using the describing function method. The maximum stable input limits for third-, fourth- and fifth-order Chebyshev Type II based Delta-Sigma modulators are established. These results are useful for optimising the design of higher-order Delta-Sigma modulators","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124935976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Implementation and analysis of microwave switch in CMOS-MEMS technology 微波开关在CMOS-MEMS技术中的实现与分析
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693077
H. Hsu, C. Dai, Ming-Ming Hsieh, Ming-Chang Tsai, Hsuan-Jung Peng
{"title":"Implementation and analysis of microwave switch in CMOS-MEMS technology","authors":"H. Hsu, C. Dai, Ming-Ming Hsieh, Ming-Chang Tsai, Hsuan-Jung Peng","doi":"10.1109/ISCAS.2006.1693077","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693077","url":null,"abstract":"The fabrication of a micro-machined microwave switch using the standard 0.35mum CMOS process and the post-process by wet etching without extra mask is implemented in this work. The components of the microwave switch are coplanar waveguide (CPW) transmission lines, a suspended membrane and supported springs. Experimental results show that the driving voltage of the switch approximates to 17 V. The switch has an insertion loss of -1.5 ~ -2.5dB and an isolation of -5 ~ -15 dB between 30 ~ 50 GHz. Moreover, an equivalent circuit is proposed to analyse the performance of this switch","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125005872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Algorithm and implementation of signed-binary recoding with asymmetric digit sets for elliptic curve cryptosystems 椭圆曲线密码系统非对称数字集的符号二进制编码算法与实现
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693713
Xiaoyu Ruan, R. Katti, David Hinkemeyer
{"title":"Algorithm and implementation of signed-binary recoding with asymmetric digit sets for elliptic curve cryptosystems","authors":"Xiaoyu Ruan, R. Katti, David Hinkemeyer","doi":"10.1109/ISCAS.2006.1693713","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693713","url":null,"abstract":"Signed-binary representations of integer k with symmetric digit set Dscr<sub>s</sub> - {-(2<sup>w</sup> - 1 ),-(2<sup>w</sup>-3),... ,-1,0,1,... ,2<sup>w</sup> - 3,2<sup>w</sup> - 1} may have lower weight than the unsigned-binary expansion of k. The \"weight\" is the number of nonzero digits in a binary expansion. Lower weight leads to fewer number of addition operations in the scalar multiplication, kP, of elliptic curve cryptosystems. Here P is a point on an elliptic curve. On the other hand, computing the minimum-weight signed-binary representation from left (most significant bit) to right (least significant bit) significantly reduces memory requirements because intermediate results do not need to be stored. Since the size of Dscr<sub>s</sub> is 2<sup>w</sup> + 1, a (w + 1)-bit data bus is necessary to represent the 2<sup>w</sup> + 1 elements in Dscr <sub>s</sub>. This is inefficient because a (w + 1)-bit bus is capable of denoting 2<sup>w+1</sup> cases. We present a new signed-binary recoding algorithm with asymmetric digit set Dscr<sub>a</sub> - {-(2<sup>w</sup> - 1),-(2<sup>w</sup> - 3),...,-1, 0,1,...,2<sup>w</sup> - 3}. For w = 2, our simulation results show that the average weight of signed-binary numbers with digit set {- 3,-1,0,1} is 0.285 times the length of their unsigned-binary expansions. For the optimal representations with {-1,0,1} the average ratio is 0.333. The number of additions is decreased by 14.4%. The encoding circuit requires 7 flip-flops and 22 gates to realize","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126003399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multilevel flash memory on-chip error correction based on trellis coded modulation 基于栅格编码调制的多电平闪存片上纠错
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692867
Fei Sun, S. Devarajan, K. Rose, Tong Zhang
{"title":"Multilevel flash memory on-chip error correction based on trellis coded modulation","authors":"Fei Sun, S. Devarajan, K. Rose, Tong Zhang","doi":"10.1109/ISCAS.2006.1692867","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692867","url":null,"abstract":"This paper presents a multilevel (ML) flash memory on-chip error correction system design based on the concept of trellis coded modulation (TCM). This is motivated by the non-trivial modulation process in ML memory storage and the effectiveness of TCM on integrating coding with modulation to provide better performance. Using code storage 2bits/cell flash memory as a test vehicle, the effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost, and operation latency, has been successfully demonstrated","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126190266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Power-oriented delay budgeting for combinational circuits 面向功率的组合电路延迟预算
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693264
Jialin Mi, Chunhong Chen, H. Kwan
{"title":"Power-oriented delay budgeting for combinational circuits","authors":"Jialin Mi, Chunhong Chen, H. Kwan","doi":"10.1109/ISCAS.2006.1693264","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693264","url":null,"abstract":"In this paper we propose an approach of providing the best power-delay tradeoff for combinational circuits. This is done by so-called power-oriented delay budgeting which is to combine the delay-budgeting technique with aggressive power optimization. We discuss the impacts that both discrete cell library and circuit topology may have on the potential power reduction. Experimental results show that up to 65% (an average of 35%) power savings can be achieved without any delay penalty","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123278461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An open-source based DSP with enhanced multimedia-processing capacity for embedded applications 基于开源的DSP，增强了嵌入式应用的多媒体处理能力
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692741
Songping Mai, Kun Yang, Wenli Lan, Chun Zhang, Zhihua Wang
{"title":"An open-source based DSP with enhanced multimedia-processing capacity for embedded applications","authors":"Songping Mai, Kun Yang, Wenli Lan, Chun Zhang, Zhihua Wang","doi":"10.1109/ISCAS.2006.1692741","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692741","url":null,"abstract":"This paper proposes an open-source based 32-bit digital signal processor (DSP) suitable for embedded multimedia processing applications. The DSP is a MIPS-based scalar RISC with Harvard micro architecture, 5-stage integer pipeline and enhanced multimedia-processing capacity. It features a data path including non-aligned data access mechanism, two-dimensional DMA function and separated embedded instruction and data memories. This special architecture greatly promotes execution efficiency of boundary-crossed and block data access operations often found in multimedia processing. The processor achieves 80-MIPS performance with typical power dissipation of 88 mW. The prototype has been fabricated using UMC 0.18mum n-well 1P6M standard CMOS technology","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123523034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Techniques for improving block error rate of LDPC decoders 提高LDPC解码器分组错误率的技术
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1693071
Xia Zheng, F. Lau, C. Tse, Simon C. Wong
{"title":"Techniques for improving block error rate of LDPC decoders","authors":"Xia Zheng, F. Lau, C. Tse, Simon C. Wong","doi":"10.1109/ISCAS.2006.1693071","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1693071","url":null,"abstract":"In the study of low-density-parity-check (LDPC) codes, most researchers are interested in their bit error rate performance. However, block error rate (BLER) is another important measure of the system performance because it provides the rate at which the blocks/packets need to be re-sent again - the smaller the better. In this paper, we apply a simple feedback technique to the decoding of LDPC codes. Extensive simulations have been performed. Results show that the proposed method can effectively improve the BLER of the codes at the waterfall region while not degrading the BER performance at the high SNR region","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123555393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Optimal distance estimation for the spectral efficiency of an hybrid cellular DS/SFH CDMA system 混合蜂窝DS/SFH CDMA系统频谱效率的最优距离估计
2006 IEEE International Symposium on Circuits and Systems Pub Date : 2006-05-21 DOI: 10.1109/ISCAS.2006.1692846
P. Varzakas
{"title":"Optimal distance estimation for the spectral efficiency of an hybrid cellular DS/SFH CDMA system","authors":"P. Varzakas","doi":"10.1109/ISCAS.2006.1692846","DOIUrl":"https://doi.org/10.1109/ISCAS.2006.1692846","url":null,"abstract":"An hybrid direct-sequence/slow frequency hopping code-division multiple-access (DS/SFH-CDMA) system operating in Rayleigh fading is described and its spectral efficiency is estimated in terms of the theoretically achievable average channel capacity (in the sense of information theory) per user. The analysis covers the operation over a broadcast cellular time-varying link and leads to a simple novel closed-form expression for the optimal distance from the base station based on the maximization of the achieved spectral efficiency","PeriodicalId":423693,"journal":{"name":"2006 IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123695218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书