2018 IEEE 27th North Atlantic Test Workshop (NATW)最新文献

One more time! Increasing fault detection with scan shift capture 再来一次!增加故障检测扫描移位捕获

2018 IEEE 27th North Atlantic Test Workshop (NATW) Pub Date : 2018-05-07 DOI: 10.1109/NATW.2018.8388862

Hui Jiang, Fanchen Zhang, Yi Sun, Jennifer Dworak

引用次数: 2

Enabling fast process variation and fault simulation through macromodelling of analog components 通过模拟组件的宏观建模实现快速过程变化和故障模拟

2018 IEEE 27th North Atlantic Test Workshop (NATW) Pub Date : 2018-05-07 DOI: 10.1109/NATW.2018.8388861

Mehmet Ince, E. Yilmaz, S. Ozev

{"title":"Enabling fast process variation and fault simulation through macromodelling of analog components","authors":"Mehmet Ince, E. Yilmaz, S. Ozev","doi":"10.1109/NATW.2018.8388861","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388861","url":null,"abstract":"With the advent of built-in self-test (BIST) in analog and RF circuits, it is essential that the fault coverage of potential BIST solutions be evaluated before they are deployed. However, large scale fault simulations are often infeasible even when considering the extensive computational power available today. Fault simulations are more challenging for devices that contain frequency transformation, such as phased locked loops (PLLs) or mixers. Thus, a mixed-mode simulation is necessary that captures fault behavior at the lower levels of the hierarchy and propagates this information to the system-level. Mixed-mode simulators, such as Verilog-A, can be used for evaluating nominal circuit behavior but falls short when evaluating faulty circuit behavior. This paper presents a macro modeling approach for mixed-signal circuits through a case study of voltage controlled oscillators (VCOs) used in PLLs. The evaluated BIST technique is the measurement of the phase transfer function from the input to the output. This requires a long transient simulation due to the need to capture the high frequency behavior of the PLL while covering the settling time of the low-frequency filter and VCO input. As the ratio of the output to the input frequency increases, simulation time also increases, making the analyses prohibitively expensive for some cases. In this paper, we build a MATLAB/Simulink model of the VCO and PLL, which is also designed and simulated at the transistor level using the FinFET technology. By modeling free running frequency, sensitivity, duty cycle, non-linearity, and phase noise characteristic of the VCO, we show that both PLL simulations, one using Spice, and one using the proposed macromodeling technique along with Simulink, match in response whereas the proposed approach only takes a fraction of time of Spice simulations.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"339 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122753913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Case study on low pin count testing of industry transceiver chip 工业收发芯片低引脚数测试实例研究

2018 IEEE 27th North Atlantic Test Workshop (NATW) Pub Date : 2018-05-01 DOI: 10.1109/NATW.2018.8388868

Imtiaz Ahmed, Subhash Baraiya, Rahul Singhal

引用次数: 0

Nanoscale silicon mosfet response to THz radiation for testing VLSI 用于超大规模集成电路测试的纳米硅mosfet对太赫兹辐射的响应

2018 IEEE 27th North Atlantic Test Workshop (NATW) Pub Date : 2018-05-01 DOI: 10.1109/NATW.2018.8388865

M. Shur, J. Suarez

引用次数: 8

Reducing test time with FPGA accelerators using OpenCL 使用OpenCL减少FPGA加速器的测试时间

2018 IEEE 27th North Atlantic Test Workshop (NATW) Pub Date : 2018-05-01 DOI: 10.1109/NATW.2018.8388864

Timothy M. Platt, Chen Liu

引用次数: 3

New testing approach using near electromagnetic field probing intending to upgrade in-circuit testing of high density PCBAs 近电磁场探测是一种新的测试方法，旨在提高高密度pcb的在线测试水平

2018 IEEE 27th North Atlantic Test Workshop (NATW) Pub Date : 2018-05-01 DOI: 10.1109/NATW.2018.8388867

Nabil El Belghiti Alaoui, P. Tounsi, A. Boyer, A. Viard

{"title":"New testing approach using near electromagnetic field probing intending to upgrade in-circuit testing of high density PCBAs","authors":"Nabil El Belghiti Alaoui, P. Tounsi, A. Boyer, A. Viard","doi":"10.1109/NATW.2018.8388867","DOIUrl":"https://doi.org/10.1109/NATW.2018.8388867","url":null,"abstract":"With the density increase of today's printed circuit board assemblies (PCBA), the electronic test methods reached their limits, in the same time the requirements of high reliability and robustness are greater. Original equipment manufacturers are obliged to reduce the number of physical test points and to find better-adapted test methods. Current test methods must be rethought to include a large panel of physical phenomena that can be used to detect electrical defects of components, absence, wrong value, and shorts at component level on the board under test (BUT). We will present the possibility of using electromagnetic signature to diagnose faulty components contactlessly. The technique consists in using small diameter near electromagnetic field probes, which detect the field distribution over powered sensitive components. A giant magnetoresistance (GMR) sensor was used as well to detect variations in low frequency components. The loading of the BUT is specifically chosen to enhance the sensitivity of the EM measurements. Reference EM signatures are extracted from a fault-free circuit, which will be compared to those extracted from a sample PCBA in which we introduced a component level defect by removing or changing the value of critical components. As a result, we will show that the amplitude of a specific harmonic acts as a sensing parameter, which is accurately related to the variation of the component value.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126035460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A simplified on-chip calibration method for branch-line coupler 一种简化的支路耦合器片上标定方法

2018 IEEE 27th North Atlantic Test Workshop (NATW) Pub Date : 2018-05-01 DOI: 10.1109/NATW.2018.8388863

Wei Jiang, Guoan Wang

引用次数: 2

An analysis of an inexpensive memory test solution 一个廉价的内存测试解决方案的分析

2018 IEEE 27th North Atlantic Test Workshop (NATW) Pub Date : 2018-05-01 DOI: 10.1109/NATW.2018.8388866

Ryan Pennucci, R. Jurasek, W. Hokenmaier, L. Patrick, J. Bucci, D. Labrecque, Dave Kinney

引用次数: 0