一个廉价的内存测试解决方案的分析

2018 IEEE 27th North Atlantic Test Workshop (NATW) Pub Date : 2018-05-01 DOI:10.1109/NATW.2018.8388866

Ryan Pennucci, R. Jurasek, W. Hokenmaier, L. Patrick, J. Bucci, D. Labrecque, Dave Kinney

{"title":"一个廉价的内存测试解决方案的分析","authors":"Ryan Pennucci, R. Jurasek, W. Hokenmaier, L. Patrick, J. Bucci, D. Labrecque, Dave Kinney","doi":"10.1109/NATW.2018.8388866","DOIUrl":null,"url":null,"abstract":"Multi-project wafers have lowered manufacturing costs for semiconductor prototypes, yet test costs remain high, presenting a barrier for innovation in the market. We present and analyze a low-cost test strategy for memory devices.","PeriodicalId":423190,"journal":{"name":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An analysis of an inexpensive memory test solution\",\"authors\":\"Ryan Pennucci, R. Jurasek, W. Hokenmaier, L. Patrick, J. Bucci, D. Labrecque, Dave Kinney\",\"doi\":\"10.1109/NATW.2018.8388866\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multi-project wafers have lowered manufacturing costs for semiconductor prototypes, yet test costs remain high, presenting a barrier for innovation in the market. We present and analyze a low-cost test strategy for memory devices.\",\"PeriodicalId\":423190,\"journal\":{\"name\":\"2018 IEEE 27th North Atlantic Test Workshop (NATW)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 27th North Atlantic Test Workshop (NATW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NATW.2018.8388866\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 27th North Atlantic Test Workshop (NATW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NATW.2018.8388866","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

多项目晶圆降低了半导体原型的制造成本，但测试成本仍然很高，这对市场创新构成了障碍。我们提出并分析了一种低成本的存储设备测试策略。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An analysis of an inexpensive memory test solution

Multi-project wafers have lowered manufacturing costs for semiconductor prototypes, yet test costs remain high, presenting a barrier for innovation in the market. We present and analyze a low-cost test strategy for memory devices.

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来源期刊

2018 IEEE 27th North Atlantic Test Workshop (NATW)

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