Reducing test time with FPGA accelerators using OpenCL

Abstract

The cost of semiconductor test is often strongly related to the die test time. Reducing this time is always a goal for both the fab customer as well as the semiconductor test house. Techniques to achieve test time reduction have included the use of dedicated hardware to perform certain test functions. While these techniques are effective, they can be time consuming to develop and this effort is often a deterrent to their development and use. This paper describes how a Field Programmable Gate Array (FPGA) accelerator can be used to process wafer test data. Historically, the use of FPGAs required a skilled digital designer to create the necessary logic to implement the intended test processing hardware. With OpenCL, however, the addition of hardware acceleration can be accomplished with traditional software coding. The amount of time required to deliver the test solution can be reduced from multiple weeks (or longer) to just a few days. With OpenCL, the ability to use hardware acceleration is brought to test engineers who do not have skills to designs FPGA logic.