Case study on low pin count testing of industry transceiver chip

Abstract

IC designs have been growing exponentially in size but the number of pins have not kept the same pace. This imbalance poses a difficult challenge when a design has very limited number of test pins but still requires a high quality testing. This problem is exacerbated when additional fault models like transition delay fault model are required for testing. This paper describes how a low pin count test controller was able to meet all these requirements to test a pin limited transceiver chip used in Qualcomm Technologies Inc.'s state-of-the-art chipset. The low pin count test controller supports at-speed testing with on-chip clock controller and exceeded the test coverage requirements for both stuck-at and at-speed testing by 1.22% and 2.16% respectively. During wafer testing, this test-pin savings enabled higher parallel testing of dies using multi-site testing which reduced the test-costs by about 1.6x.