Shun-Chieh Lin, Jia-Ching Wang, Hsueh-Wei Yang, Jhing-Fa Wang
{"title":"Hardware-software co-design of a speech translation embedded system","authors":"Shun-Chieh Lin, Jia-Ching Wang, Hsueh-Wei Yang, Jhing-Fa Wang","doi":"10.3233/JEC-2009-0085","DOIUrl":"https://doi.org/10.3233/JEC-2009-0085","url":null,"abstract":"Previous research has shown that there are two architectures for speech-to-speech translation (S2ST) system implementation. One is client-server based systems that are built on the server computer, which means they are not available anytime or anywhere. The other is portable stand-alone devices, which lack real-time performance. Therefore, this work presents a hardware-software co-design of a speech translation embedded system for portable S2ST applications. This system is characterized by small size, low cost, real-time operation, and high portability. In order to realize the proposed S2ST system, we have designed the ARM-based system-on-a-programmable-chip (SoPC) architecture, the speech translation intellectual property, and the software procedures of the proposed SoPC. The entire design was implemented on ALTERA EPXA10. The English-to-Mandarin translation process can be completed within 0.5 second at a 40 MHz clock frequency with 1,200 translation patterns. The maximum frequency is 46.22 MHz, and the usage of logic elements is 19,318 (50% of the total number of logic elements of the EPXA10 device).","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124044386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. M. Reason, Han Chen, C. Jung, SooYeon Kim, Paul B. Chou, Kangyoon Lee
{"title":"A framework for managing the life-cycle of event-driven, embedded applications","authors":"J. M. Reason, Han Chen, C. Jung, SooYeon Kim, Paul B. Chou, Kangyoon Lee","doi":"10.3233/JEC-2009-0082","DOIUrl":"https://doi.org/10.3233/JEC-2009-0082","url":null,"abstract":"Event-driven, embedded applications that embody the composition of many disparate components are emerging as an important class of pervasive applications. Realizing such applications often requires a breadth of expertise across many disciplines; consequently, managing the life cycle for this class of applications can be a very complex, time-intensive process. In this paper, we present a framework that eases the complexity of managing the life cycle of event-driven, embedded applications. We call this framework Rapid Integrated Solution Enablement or RISE. For solution creation, component composition and software reuse are two central concepts of RISE. Solutions in RISE are graphically composed from reusable components using a visual editor. For deployment and management of solutions, we exploit the concept of dynamic and remote deployment of components from the Open Service Gateway Initiative (OSGi). We describe the RISE architecture and discuss our prototype implementation, which follows the model-driven methodology and leverages open source technologies, such as Eclipse. Additionally, we illustrate the efficacy of RISE with an example solution for RFID supply chain logistics.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126295233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC","authors":"Pao-Ann Hsiung, Chun-Hsian Huang, Yuan-Hsiu Chen","doi":"10.3233/JEC-2009-0078","DOIUrl":"https://doi.org/10.3233/JEC-2009-0078","url":null,"abstract":"Existing operating systems can manage the execution of software tasks efficiently, however the manipulation of hardware tasks is very limited. In the research on the design and implementation of an embedded operating system that manages both software and hardware tasks in the same framework, two major issues are the dynamic scheduling and the dynamic placement of hardware tasks into a reconfigurable logic space in an SoC . The distinguishing criteria for good dynamic scheduling and placement methods include the total schedule length and the amount of fragmentation incurred while tasks are dynamically placed and replaced. Existing methods either do not take fragmentation into consideration or postpone the consideration of fragmentation to a later stage of space allocation. In our method, we try to reduce fragmentation during placement itself. The advantage of such an approach is that not only the reconfigurable space is utilized more efficiently, but the total schedule length is also reduced, that is, hardware tasks complete faster. Experimental results on large random tasks sets have shown that the proposed improvement is as much as 23.3% in total fragmentation and 2.0% in total schedule time.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126261757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Embed. Comput.Pub Date : 2005-08-01DOI: 10.1007/978-3-540-39762-5_47
T. Aa, M. Jayapala, F. Barat, Geert Deconinck, R. Lauwereins, H. Corporaal, F. Catthoor
{"title":"Instruction buffering exploration for low energy embedded processors","authors":"T. Aa, M. Jayapala, F. Barat, Geert Deconinck, R. Lauwereins, H. Corporaal, F. Catthoor","doi":"10.1007/978-3-540-39762-5_47","DOIUrl":"https://doi.org/10.1007/978-3-540-39762-5_47","url":null,"abstract":"","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121834788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Guillon, F. Rastello, Thierry Bidault, Florent Bouchez
{"title":"Procedure placement using temporal-ordering information: dealing with code size expansion","authors":"C. Guillon, F. Rastello, Thierry Bidault, Florent Bouchez","doi":"10.1145/1023833.1023870","DOIUrl":"https://doi.org/10.1145/1023833.1023870","url":null,"abstract":"In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache conflicts can be partially handled at linked time by procedure placement. Pettis and Hansen give in [1] an algorithm that reorders procedures in memory by aggregating them in a greedy fashion. The Gloy and Smith algorithm [2] greatly decreases the number of con ict-misses but increases the code size by allowing gaps between procedures. The latter contains two main stages: the cache-placement phase assigns modulo addresses to minimizes cache-conflicts; the memory-placement phase assigns final memory addresses under the modulo placement constraints, and minimizes the code size expansion. In this paper: (1) we state the NP-completeness of the cache-placement problem; (2) we provide an optimal algorithm to the memory-placement problem with complexity O(n min(n; L) log* (n)) (n is the number of procedures, L the cache size); (3) we take final program size into consideration during the cache-placement phase. Our modifications to the Gloy and Smith algorithm gives on average a code size expansion of 8% over the original program size, while the initial algorithm gave an expansion of 177%. The cache miss reduction is nearly the same as the Gloy and Smith solution with 35% cache miss reduction.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116079890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Embed. Comput.Pub Date : 2003-12-01DOI: 10.1007/978-3-540-39762-5_34
S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas
{"title":"Instruction level energy modeling for pipelined processors","authors":"S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas","doi":"10.1007/978-3-540-39762-5_34","DOIUrl":"https://doi.org/10.1007/978-3-540-39762-5_34","url":null,"abstract":"","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116623942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Huthaifa Al-Omari, C. Papachristou, F. Wolff, D. R. McIntyre
{"title":"Smoothing delay jitter in networked control systems","authors":"Huthaifa Al-Omari, C. Papachristou, F. Wolff, D. R. McIntyre","doi":"10.3233/JEC-2009-0103","DOIUrl":"https://doi.org/10.3233/JEC-2009-0103","url":null,"abstract":"Delay jitter is a critical factor that must be considered in many real-time applications that require accurate prediction of packet delivery times. Delay jitter can be smoothed by holding packets in a play-back buffer for a certain time called a play-back delay. In this paper, we extensively examine the new scheme that we have proposed in [1] to enhance the prediction of the play-back delay in Networked Control Systems (NCSs). Our newly proposed scheme differs from previous schemes by using the one way delay variation that we have studied its behavior by conducting extensive measurements between fifty strategically located wired and wireless connected hosts. The advantages of our scheme are that it predicts sudden delay spikes, provides a closer approximation to the round trip time (RTT), and exhibits less frequent outliers.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117162390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A routing algorithm for multicast on hypercube multi-core architecture","authors":"Yuxin Wang, He Guo, Liye Yuan","doi":"10.3233/JEC-2009-0104","DOIUrl":"https://doi.org/10.3233/JEC-2009-0104","url":null,"abstract":"This paper presents an effective approach using synchronous parallel transmission worm-switching supporting multicast services on hypercube multi-core architecture. Hypercube is a flexible interconnection structure and multi-cast packets on it are routed and scheduled among multi-cores using a local identity routing algorithm. The identity ID attached to every flit allows different flits to be mixed in the same queue. In internal nodes, LUT decides the direction of flits and RU records the transmitting direction. Then switch arbiter decides what can pass the outgoing links and what have to wait. Polling-transmission policy is used to solve the deadlock problem.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132279038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Coverage-aware sensor engagement in dense sensor networks","authors":"Jun Lu, L. Bao, T. Suda","doi":"10.3233/JEC-2009-0074","DOIUrl":"https://doi.org/10.3233/JEC-2009-0074","url":null,"abstract":"Wireless sensor networks are capable of carrying out surveillance missions for various applications in remote areas without human interventions. An essential issue of sensor networks is to search for the balance between the limited battery supply and the desired lifetime of network operations. Beside data communication between sensors, maintaining sufficient surveillance, or sensing coverage, over a target region by coordination within the network is critical for many sensor networks due to the limited supply of energy source for each sensor. This paper presents a novel sensor network coverage maintenance protocol, called Coverage-Aware Sensor Engagement (CASE), to efficiently maintain the required degree of sensing coverage by activating a small number of sensors while putting the others to sleep mode. Different from other coverage maintenance protocols, CASE schedules active/inactive sensing states of a sensor according to the sensor's contribution to the network sensing coverage, therefore preserving the expected behavior of the sensor network. Coverage contribution of each sensor is quantitatively measured by a metric called \"coverage merit\". By activating sensors with relatively large coverage merit and deactivating those with small coverage merit, CASE effectively achieves energy conservation while maintaining sufficient sensor network coverage. We provide simulation results to show that CASE considerably improves the energy efficiency of coverage maintenance with low communication overhead.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128607313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}