J. Embed. Comput.最新文献_第2页

A system-level design methodology for application-specific networks-on-chip 用于特定于应用程序的片上网络的系统级设计方法

J. Embed. Comput. Pub Date : 2009-08-01 DOI: 10.3233/JEC-2009-0089

A. Bartzas, Lazaros Papadopoulos, D. Soudris

引用次数: 1

Power profile estimation and compiler-based software optimization for mobile devices 移动设备的功耗估计和基于编译器的软件优化

J. Embed. Comput. Pub Date : 2009-08-01 DOI: 10.3233/JEC-2009-0095

M. Grumer, M. Wendt, C. Steger, R. Weiss, U. Neffe, Andreas Mühlberger

引用次数: 1

Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses 片上总线均匀温度分布的改进开关活动平衡编码方案

J. Embed. Comput. Pub Date : 2009-08-01 DOI: 10.3233/JEC-2009-0088

P. Sithambaram, A. Macii, E. Macii

{"title":"Enhanced switching activity balancing encoding schemes for uniform temperature distribution in on-chip buses","authors":"P. Sithambaram, A. Macii, E. Macii","doi":"10.3233/JEC-2009-0088","DOIUrl":"https://doi.org/10.3233/JEC-2009-0088","url":null,"abstract":"With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important. One way to mitigate these effects is to ensure uniform switching of bus wires. This prevents the unusual heating of some wires causing gradients, leading to various undesired effects. Thermal Spreading has shown to be a successful approach to bus temperature minimization. The idea at the basis of this technique is that of periodically permuting the routing of input bitstreams to the various bus lines, with the objective of temporally and spatially distributing the number of transitions over the entire bus. This prevents high switching activities from pertaining only to a few lines which causes an unnatural increase in temperature. In this paper, we propose new encoding schemes which improve the capability of the Thermal Spreading approach of balancing switching activities over the bus wires. The solutions we introduce are adaptive and dynamic in nature, as they select the bitstream and it's appropriate bus line based on online monitoring of actual bus traffic. This is possible thanks to some ad-hoc hardware unit running in parallel at the transmitting and receiving ends of the bus. Our experimental results show that, on average, the proposed encoding schemes improve the transition balancing capabilities of Thermal Spreading by a significant amount.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129614319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Direct memory access usage optimization in network applications for reduced memory latency and energy consumption 网络应用程序中的直接内存访问使用优化，以减少内存延迟和能耗

J. Embed. Comput. Pub Date : 2009-08-01 DOI: 10.3233/JEC-2009-0096

A. Bartzas, Miguel Peón Quirós, S. Mamagkakis, F. Catthoor, D. Soudris, J. Mendias

{"title":"Direct memory access usage optimization in network applications for reduced memory latency and energy consumption","authors":"A. Bartzas, Miguel Peón Quirós, S. Mamagkakis, F. Catthoor, D. Soudris, J. Mendias","doi":"10.3233/JEC-2009-0096","DOIUrl":"https://doi.org/10.3233/JEC-2009-0096","url":null,"abstract":"Today, wireless networks are becoming increasingly ubiquitous. Usually several complex multi-threaded applications are mapped on a single embedded system and each of them is triggered by a different input stream (in accordance with the run-time behaviours of the user and the environment). This dynamicity renders the task of fully analyzing at design-time these systems very complex, if not impossible. Therefore, run-time information has to be used in order to produce an efficient design. This introduces new challenges, especially for embedded system designers using a Direct Memory Access (DMA) module, who have to know in advance the memory transfer behaviour of the whole system, in order to design and program their DMA efficiently. This is especially important in embedded systems with DRAM memories as the concurrent accesses from different processing elements can adversely affect the page-based architecture of these memory elements. Even more, the increasingly common usage of dynamic data types further complicates the problem because the exact location of data instances in the memory is unknown at design-time. In this paper we propose a system-level optimization methodology to adapt the DMA usage parameters automatically at run-time, according to online information. With our proposed optimization approach we manage to reduce the mean latency of the memory transfers by more than 18%, thus reducing the average number of cycles that processing elements or DMAs have to waste waiting for data from the main memory, while optimizing energy consumption and system responsiveness. We evaluate our approach using a set of real-life applications and real wireless dynamic streams.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126733306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Timing margin evaluation with a simple statistical timing analysis flow 时序裕度评估具有简单的时序统计分析流程

J. Embed. Comput. Pub Date : 2009-08-01 DOI: 10.3233/JEC-2009-0094

V. Migairou, Robin Wilson, S. Engels, Zeqin Wu, N. Azémard, P. Maurine

引用次数: 0

Clock-tree synthesis for low-EMI design 低电磁干扰设计的时钟树合成

J. Embed. Comput. Pub Date : 2009-08-01 DOI: 10.3233/JEC-2009-0092

D. Pandini, G. Repetto, Vincenzo Sinisi

{"title":"Clock-tree synthesis for low-EMI design","authors":"D. Pandini, G. Repetto, Vincenzo Sinisi","doi":"10.3233/JEC-2009-0092","DOIUrl":"https://doi.org/10.3233/JEC-2009-0092","url":null,"abstract":"In modern digital ICs, the increasing demand for performance and throughput requires higher operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip clock signals with fast rise/fall times are among the most detrimental sources of electromagnetic (EM) noise, since not only they generate radiated emissions, but they also have a large impact con the conducted emissions, as the power rail noise localized in close proximity of the toggling clock edges propagates to the board through the power and ground I/O pads. In this work, we analyze the impact of different clock distribution solutions on the spectral content of typical on-chip waveforms, in order to develop an effective methodology for EMC-aware clock-tree synthesis, which globally reduces the EM emissions. Our approach can be seamlessly integrated into a typical design flow, and its effectiveness is demonstrated with experimental results obtained from the clock distribution network of an industrial digital design.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123534471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Asymmetry-aware link layer services in wireless sensor networks 无线传感器网络中链路层服务的不对称感知

J. Embed. Comput. Pub Date : 2009-04-01 DOI: 10.3233/JEC-2009-0087

Junzhao Du, Weisong Shi, Kewei Sha

{"title":"Asymmetry-aware link layer services in wireless sensor networks","authors":"Junzhao Du, Weisong Shi, Kewei Sha","doi":"10.3233/JEC-2009-0087","DOIUrl":"https://doi.org/10.3233/JEC-2009-0087","url":null,"abstract":"Recent studies in wireless sensor networks (WSNs) have observed that the irregular link quality is a common phenomenon, rather than an anomaly. The irregular link quality, especially link asymmetry, has significant impacts on the design of WSN protocols. In this paper, we propose two asymmetry-aware link layer services, including the neighborhood link quality service (NLQS) and the link relay service (LRS). The novelty of the NLQS service is taking the link asymmetry into consideration, providing timeliness link quality and distinguishing the inbound and outbound neighbors with the support of LRS, which builds a relay framework to alleviate the effects of link asymmetry. To demonstrate the proposed link layer service, we design and implement two example applications, building the shortest-hop routing path (SHRT) and the best path reliability routing path (BRRT), on the TinyOS platform. We found that the performance of two example applications is improved substantially. More than 40% of nodes identify more outbound neighbors and the percentage of increased outbound neighbors is between 14% and 100%. In SHRT, more than 15% of nodes reduce hops of the routing path and the percentage of reduced hops is between 14% and 100%. In BRRT, more than 16% of nodes improve the path reliability of the routing path and the percentage of the improved path reliability is between 2% to 50%.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121419380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

FPGA-based ROM-free network intrusion detection using shift-OR circuit 基于fpga的移或电路的无rom网络入侵检测

J. Embed. Comput. Pub Date : 2009-04-01 DOI: 10.3233/JEC-2009-0083

Wen-Jyi Hwang, Huang-Chun Roan, Ying-Nan Shih, D. Lo, C. Ou

引用次数: 3

A low-power baseband modem architecture for a mobile RFID reader 一种用于移动RFID阅读器的低功耗基带调制解调器架构

J. Embed. Comput. Pub Date : 2009-04-01 DOI: 10.3233/JEC-2009-0086

Seokjoong Hwang, J. Lee, Seon Wook Kim, Jihun Koo, WooShik Kang

{"title":"A low-power baseband modem architecture for a mobile RFID reader","authors":"Seokjoong Hwang, J. Lee, Seon Wook Kim, Jihun Koo, WooShik Kang","doi":"10.3233/JEC-2009-0086","DOIUrl":"https://doi.org/10.3233/JEC-2009-0086","url":null,"abstract":"Currently the RFID (Radio Frequency IDentification) systems become used in many areas, especially for delivery, manufacturing, and maintenance of goods. For example, a tag reader or a tag interrogator communicates with tags attached on goods, reads their identification codes, and accesses their related database through a network infrastructure. This approach makes it easy to maintain goods very efficiently in large-scale markets, delivery systems, and so on. There are many research activities in RFID systems for industrial applications, but there is few on mobile and portable devices such as cellular phones and PDAs. This paper presents an architecture overview of a multi-protocol RFID reader on mobile devices with detailed description of hardware implementation. We have considered several design parameters, such as low power consumption, cost effectiveness and flexibility. Also, since our architecture supports WIPI (Wireless Internet Platform for Interoperability), any WIPI application can use our RFID reader's functionalities to query tags' information from Internet through HAL interfaces. We prototyped our system on the ARM-based Excalibur FPGA with iPAQ PDA, and also a chip with 0.18~um technology for verification of our architecture.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134263762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Energy minimization for heterogeneous wireless sensor networks 异构无线传感器网络的能量最小化

J. Embed. Comput. Pub Date : 2009-04-01 DOI: 10.3233/JEC-2009-0084

Meikang Qiu, C. Xue, Z. Shao, Meilin Liu, E. Sha

引用次数: 18