Wen-Jyi Hwang, Huang-Chun Roan, Ying-Nan Shih, D. Lo, C. Ou
{"title":"基于fpga的移或电路的无rom网络入侵检测","authors":"Wen-Jyi Hwang, Huang-Chun Roan, Ying-Nan Shih, D. Lo, C. Ou","doi":"10.3233/JEC-2009-0083","DOIUrl":null,"url":null,"abstract":"This paper introduces a novel FPGA-based signature match co-processor that can serve as the core of a hardware-based network intrusion detection system (NIDS). The co-processor is based on simple shift registers and bitmap encoders for the efficient signature match in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.","PeriodicalId":422048,"journal":{"name":"J. Embed. Comput.","volume":"88 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"FPGA-based ROM-free network intrusion detection using shift-OR circuit\",\"authors\":\"Wen-Jyi Hwang, Huang-Chun Roan, Ying-Nan Shih, D. Lo, C. Ou\",\"doi\":\"10.3233/JEC-2009-0083\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a novel FPGA-based signature match co-processor that can serve as the core of a hardware-based network intrusion detection system (NIDS). The co-processor is based on simple shift registers and bitmap encoders for the efficient signature match in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.\",\"PeriodicalId\":422048,\"journal\":{\"name\":\"J. Embed. Comput.\",\"volume\":\"88 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"J. Embed. Comput.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.3233/JEC-2009-0083\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"J. Embed. Comput.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.3233/JEC-2009-0083","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA-based ROM-free network intrusion detection using shift-OR circuit
This paper introduces a novel FPGA-based signature match co-processor that can serve as the core of a hardware-based network intrusion detection system (NIDS). The co-processor is based on simple shift registers and bitmap encoders for the efficient signature match in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.