Hardware-software co-design of a speech translation embedded system

Abstract

Previous research has shown that there are two architectures for speech-to-speech translation (S2ST) system implementation. One is client-server based systems that are built on the server computer, which means they are not available anytime or anywhere. The other is portable stand-alone devices, which lack real-time performance. Therefore, this work presents a hardware-software co-design of a speech translation embedded system for portable S2ST applications. This system is characterized by small size, low cost, real-time operation, and high portability. In order to realize the proposed S2ST system, we have designed the ARM-based system-on-a-programmable-chip (SoPC) architecture, the speech translation intellectual property, and the software procedures of the proposed SoPC. The entire design was implemented on ALTERA EPXA10. The English-to-Mandarin translation process can be completed within 0.5 second at a 40 MHz clock frequency with 1,200 translation patterns. The maximum frequency is 46.22 MHz, and the usage of logic elements is 19,318 (50% of the total number of logic elements of the EPXA10 device).