{"title":"Computing symbolic transfer functions of analog circuits by applying pure nodal analysis","authors":"T. Esteban, Cid-Monjaraz Jaime","doi":"10.1109/ICCDCS.2002.1004007","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004007","url":null,"abstract":"A method focused on computing symbolic transfer functions (TFs) of analog circuits is presented. In order to perform a pure nodal analysis (PNA), all non-NA-compatible elements are transformed to be NA-compatible ones using nullors. A reasonable amount of computer effort is saved through applying the nullor properties in order to reduce the order of the matrix Y/sub NA/ by one for each nullor. Throughout the paper, the suitability and appropriateness of the proposed analysis technique, to be used as an analytical tool, is demonstrated.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130050815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic logic styles with improved noise-immunity","authors":"F. Mendoza-Hernandez, M. Linarea, V. Champac","doi":"10.1109/ICCDCS.2002.1004019","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004019","url":null,"abstract":"Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. Noise effects in deep submicron CMOS VLSI circuits have an importance comparable to area, delay and power consumption. To address this problem a new noise-tolerant dynamic circuit technique suitable for dynamic logic styles is presented. Simulation results show that the proposed technique improves the ANTE (Balamurugan and Shanbhag, IEEE J. Solid-State Circ., vol. 36, no. 2, pp. 273-280, 2001) by 3.4/spl times/ and 2.8/spl times/ over conventional dynamic true single-phase-clock (TSPC) and Domino logic, respectively. The improvement in the ANTE-delay quotient is 2.8/spl times/ and 2.25/spl times/ over conventional dynamic logic, 2.0/spl times/ and 1.7/spl times/ over twin-transistor technique, 1.7/spl times/ and 1.04/spl times/ over Bobba's technique for CMOS TSPC and Domino AND gates, respectively.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"12 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120967724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Rodríguez-Calderón, J. Santana-Corte, F. Sandoval-Ibarra
{"title":"Reducing non-idealities on switched-current sigma-delta modulators","authors":"R. Rodríguez-Calderón, J. Santana-Corte, F. Sandoval-Ibarra","doi":"10.1109/ICCDCS.2002.1004004","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004004","url":null,"abstract":"Oversampling /spl Sigma//spl Delta/ A/D and D/A converters based on switched current (SI) cells are an option that offers great advantages when manufactured with digital circuit processes. However, SI suffers from non-idealities that limit the performance of oversampling /spl Sigma//spl Delta/ modulators. This paper presents a conventional second order /spl Sigma//spl Delta/ modulator using the SI technique with a compensation scheme that reduces non-idealities of the integrators improving the performance of the modulator for audio applications.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120947323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Remote laboratory experiments in electrical engineering education","authors":"I. Gustavsson","doi":"10.1109/ICCDCS.2002.1004082","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004082","url":null,"abstract":"A remote or online laboratory is a laboratory where one can access experiments and instruments or other equipment from outside over the Internet. Laboratories for undergraduate education or vocational training in basic electrical engineering are easy to control remotely. One cannot see or hear the electrical current, so there is no need for sound or video transmission. Computer-based instruments do not have any control buttons or displays on the front panel. They have virtual front panels on the host computer only and those panels can be moved to a remote computer screen. However, the manual forming of circuits and connecting of test probes cannot be transferred. These actions must be performed in another way in a remote laboratory. Remotely controllable switch matrices must be used. In the remote laboratory at BTH (Blekinge Institute of Technology) a client/server architecture is used. The student makes all the settings wanted on the client computer and then sends them to a lab server. The server makes measurements requested and returns the data obtained. The whole procedure takes only a second or two. A number of clients can access the experiments simultaneously. The laboratory is used in ordinary courses for on-campus students. They access the laboratory from a computer hall or from elsewhere outside the university. Due to the low number of bytes transferred, a 56 kbit modem is sufficient.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127755534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Benefits of the CORDIC-algorithm in a versatile COFDM modulator/demodulator design","authors":"S. W. Mondwurf","doi":"10.1109/ICCDCS.2002.1004111","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004111","url":null,"abstract":"Following a short description of the Fast-Fourier-Transformation (FFT) this paper discusses the advantages of the CORDIC-algorithm (Coordinate Rotation Digital Computer) compared to complex multiplication in butterfly-operations and NCOs (Numerical Controlled Oscillator) which are used in many digital transmission systems. The implementation of the CORDIC-algorithm in programmable logic devices is shown by the example of a versatile modulator for digital terrestrial television.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116466815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Circuital modeling from electronic devices to oil production","authors":"R. Callarotti","doi":"10.1109/ICCDCS.2002.1004085","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004085","url":null,"abstract":"In this paper we discuss the general topic of deriving equivalent circuits from the differential equations that determine the response of a given system. This is the procedure which is normally followed in modeling solid state devices, where the distributed parameters of the equivalent circuits are derived from the solutions to Laplace or Poisson equations. We apply the procedure to the case of the thermal excitation-through electrical heaters-of heavy oil reservoirs. The circuital visualization of this process provides insights which are extremely helpful in understanding the system response.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126076263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of pattern dependencies on copper damascene chemical mechanical polishing","authors":"Serita Narinesingh, J. Leffew, W. Moreno","doi":"10.1109/ICCDCS.2002.1004047","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004047","url":null,"abstract":"The drawbacks in using CMP on copper are well know but currently misunderstood. The purpose of this research project was to achieve a concise understanding of copper CMP issues particularly associated with pattern, surface topography and its dependencies. With the use of Lucent Technologies Bell Labs CMP tools and wafers deposited with copper and TEOS, profilometry measurements were made. These wafers had arrays of lines with varying pitch where density was kept constant. The study used a special test mask with a unique set of structures to determine the effects of pitch features. The interaction of these layout effects was carefully analyzed using polish data taken with small time-steps to capture the transition of the polish characteristics before and after the barrier was exposed. Using the data gathered from the tests on these wafers, an analysis of the copper CMP dependence on wafer pattern variations, such as pitch, was performed. The key issues, dishing and erosion, were then determined and addressed. A recommendation for better feature sizes based on certain trends for minimal erosion and dishing was developed. It was found that erosion had very little dependence on pitch variation. Dishing increased with pitch and copper line width.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130993540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Grenier, D. Dubuc, L. Rabbia, A. Tackac, P. Pons, T. Parra, P. Caudriller, H. Aubert
{"title":"MEMS devices for the future wireless applications","authors":"K. Grenier, D. Dubuc, L. Rabbia, A. Tackac, P. Pons, T. Parra, P. Caudriller, H. Aubert","doi":"10.1109/ICCDCS.2002.1004045","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004045","url":null,"abstract":"In this communication, we will outline the potentialities offered by the MEMS technologies to realize front end modules featuring attractive performances in term of noise, linearity, power consumption and compactness. Bulk micromachining techniques are used to achieve very low loss interconnects up to millimeterwave range when surface micromachining techniques are preferred to realize moveable devices. The association of bulk and surface micromachining allows to realize advanced millimeterwave microsystems. Concerning the design methods, both electromagnetic, electrical and mechanical simulation are mandatory to get accurate results.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133851247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimum design of device/circuit cooperative schemes for ultra-low power applications","authors":"T. Hiramoto","doi":"10.1109/ICCDCS.2002.1004066","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004066","url":null,"abstract":"The miniaturization of MOS transistors has been the only guideline for device design for high performance VLSIs. Approaching to the fundamental scaling limit, various critical issues have arisen in sub-100 nm CMOS devices such as the increase in power dissipation and device degradation due to short channel effects. In order to solve these problems and go into the deep sub-100 nm regime, new device design guidelines should be developed. In this paper, cooperation between device and circuit is proposed for ultra-low power applications. The optimum design in low power circuit schemes is discussed from the device point of view, especially for the suppression of stand-by power.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"20 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114287060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, V. Chowdhury
{"title":"On chip measurement of I/sub C/(V/sub BE/) characteristics for high accuracy bandgap applications","authors":"W. Rahajandraibe, C. Dufaza, D. Auvergne, B. Cialdella, B. Majoux, V. Chowdhury","doi":"10.1109/ICCDCS.2002.1004037","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004037","url":null,"abstract":"The E/sub G/ and X/sub TI/ coefficients are sufficient to completely characterise the temperature dependence of I/sub C/(V/sub BE/) relationship of bipolar transistors (BJT). They are usually obtained from measured V/sub BE/(T) values, using least square algorithm at a constant collector current. This method involves an accurate measurement of V/sub BE/ and of the operating temperature. We propose in this paper, a configurable test structure dedicated to the extraction of the temperature dependence of I/sub C/(V/sub BE/) characteristic for the BJT designed with bipolar or BiCMOS processes. This allows a direct measurement of the die temperature and consequently an accurate measurement of V/sub BE/(T). First, the classical extraction method is explained. Then, the implementation technique of the new method is discussed and finally, an improvement of a bandgap design is presented.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115585935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}