1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献_第4页

Progress with high efficiency IMPATT diodes 高效impat二极管的研究进展

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155719

J. Gewartowski

引用次数: 0

Modeling the dynamic behavior of the I2L inverter 对I2L逆变器的动态行为进行建模

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155680

W. Mattheus, R. Mertens

{"title":"Modeling the dynamic behavior of the I2L inverter","authors":"W. Mattheus, R. Mertens","doi":"10.1109/ISSCC.1977.1155680","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155680","url":null,"abstract":"r VlODE ,LS WHICH characterize 12L inverters have been presented, as well as methods to determine the model parameters’ >’. Since these models rely on the charge control principles, a quasi-static charge distribution is assumed during transient analysis. This reflectsessentially in a one-pole approximation for the small signal input impedance of the device. The deviation of this approximation from reality is a valid measure for the applicability of the charge control model, even though the latter will be used in switching problem. Measurements of the small signal input impedance of an 12L inverter a t medium and high power levels, result in curves which strongly deviate from the -20 dB/decade rolloff of the one pole approximation; Figure 1. This indicates that the chargecontrol principles are not a priori valid. It has been reported that the charge distribution in the Y direction (perpendicular to the surface) is in principle non quasi-static in the epitaxial layer3. However, straightforward analysis proves that for realistic values of the epitaxial width W and of the NN’ interface recombination velocity s, such that the product sW is much smaller than the diffusion constant of holes in the epitaxial region, the one pole model remains a good approximation in the measured frequency range4. The influence of the distributed nature of the base resistance in the X direction constitutes a second source of non quasi-static behavior; Figure 2. The general distributed network (Figure 3 insert) can be analysed by introducing the following assumptions. ( I ) The overall impedance RB and the overall small signal admittance r, and C, are uniform over the length L of the distributed network. This implies that lateral variations are ruled out by adopting mean values for RB, r, and C,. (2) The voltage dependence of r and C, along the base is neglected for the ac analysis. Computer simulations have shown that this condition limits the applicability of the results t o moderate dc biasing, such that r, < RB. ?","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126127684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Microwave GaAs power FETs

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155733

E. Belohoubek

引用次数: 0

Design and technology for DMOS E/D logic DMOS E/D逻辑的设计与技术

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155688

M. Declerco, T. Laurent

引用次数: 0

Integrated logic - Static induction transistor logic 集成逻辑-静态感应晶体管逻辑

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155728

J. Nishizawa, B. Wilamowski

{"title":"Integrated logic - Static induction transistor logic","authors":"J. Nishizawa, B. Wilamowski","doi":"10.1109/ISSCC.1977.1155728","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155728","url":null,"abstract":"SOLID-STATE CIRCUITS are designed to minimize both delay time and operational power. The product of these is thought t o be constant, represented by a specific figure for each type of integrated circuit. The 12L structure has been shown to operate with the lowest switching energy’. The power efficiency of the Vertical Injection Logic (VIL) structure shows a further improvement, by a factor of two. However, its fabrication requires the use of 7-8 masks’. A new logic circuit structure is proposed Static Induction Transistor Logic (SITL) utilizing the static induction transistor ( SIT)3. This logic circuit permits a further reduction in the power-delay time product (theoretically 6 x and experimentally, one order of magnitude). In the case of 12L, it is made by a 3 or 4-mask technology. The packing density can be as high as 1000 gates/cm2. In this logic structure, the SITS are used as the output transistors and the lateral bipolar PNP transistor is used as the injector, as usual, as shown in Figure 1. The SIT consists of Nt drains on the top surface of the Nepitaxial layer, a Pt gate configured on both sides of the drain on the same surface and the space charge layer formed surrounding the drain regions, Nchannels penetrating the gate region below the drains and the N+ source substrate. The channels are about 2-3 p m in diamcter and are formed by lateral P-type diffusion. The fabrication process in this case is as follows. The Nepitaxial layer is grown on the N+ substrate, having a carrier concentration of 2-3 x 1013 cm-3 and a thickness of 4-5 pm. After oxidation and photolithography, B-diffused layers were formed as the gate regions of the SIT and the emitter of the injector (the lateral transistor), followed by the second oxidation. Then, the Nf -diffusion layers are formed as drain regions, followed by the opening of contact holes in the Si02 film, using the third photolithography. After A1 evaporation, the A1 film is selectively etched, and the ring oscillator formed, as shown in Figure 2.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122176763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

I2L timing circuit without external components I2L定时电路无需外部元件

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155690

R. Muller

引用次数: 0

A multiband lumped-element varactor-tuned Gunn oscillator 一种多频带集总元变容调谐的Gunn振荡器

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155659

J. Amoss, W. Cox, L. Lopez

引用次数: 2

A high performance 4K static RAM fabricated with an advanced MOS technology 采用先进的MOS技术制造的高性能4K静态RAM

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155663

R. Pashley, W. Owen, K. Kokkonen, R. Jecmen, A. Ebel, C. Ahlquist, P. Schoen

{"title":"A high performance 4K static RAM fabricated with an advanced MOS technology","authors":"R. Pashley, W. Owen, K. Kokkonen, R. Jecmen, A. Ebel, C. Ahlquist, P. Schoen","doi":"10.1109/ISSCC.1977.1155663","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155663","url":null,"abstract":"combining MOS device scaling’ with on chip substrate bias generation’. By reducing the physical parameters of the MOS device by a fixed scaling factor, circuit density and performance were increased while decreasing active circuit power. The advanced technology uses polysilicon ate lengths under 4 p and a gate oxide thickness less than 1000 R . Shallow junctions ( < l p ) are obtained by using arsenic as the source-drain diffusant. In addition, oxide isolation and depletion load processing are employed to improve further circuit performance and density. Substrate bias is used to reduce device body effect The high performance of the MOS memory was achieved by circuit is a simple differential amplifier with dc feedback to provide for process and temperature compensation. The powerdown mode is controlled by chip enable. During powerdown (CE high), the memory array is completely deselected and the column and I/O buss is reset to a threshold below supply voltage. By balancing the internal circuitry during powerdown, it is possible to overcome the additional chip enable powerup delay and obtain a powerup access time equal to the address access time; Figure 3. Typically, the RAM accesses in 45ns and has an active power dissipation of 500mW. Powerup does not display current spikes typical of dynamic circuitry and powerdown takes less than 3011s. A summary of the device characteristics is presented in Table 1.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122418126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

A monolithic 12-bit D/A converter 单片12位D/A转换器

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155693

D. Comer

引用次数: 15

A power bipolar transistor optimized for linear performance with octave capability 一种功率双极晶体管，优化线性性能，具有倍程能力

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1977.1155716

R. Wong, J. Chen

引用次数: 1