2022 IEEE Custom Integrated Circuits Conference (CICC)最新文献_第9页

A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range 具有指数可调谐伪电阻和片上数字频率校准环路的神经记录模拟前端，在5- 500 Hz范围内实现高通截止频率的3.4%偏差

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772872

Renze Gan, Liangjian Lyu, Geng Mu, C. R. Shi

{"title":"A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range","authors":"Renze Gan, Liangjian Lyu, Geng Mu, C. R. Shi","doi":"10.1109/CICC53496.2022.9772872","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772872","url":null,"abstract":"State-of-the-art capacitively-coupled analog front-end (AFE), which acquire the different frequency band neural signals by adjusting the high-pass cutoff frequency $(mathrm{f}_{text{HP}})$, necessitates a tunable gigaohm-level (GO-level) resistor with feedback capacitor to form $mathrm{f}_{text{HP}}$. In recent advances [1]–[6], as shown in Fig. 1, there are four means to emulate a GO-level on-chip resistor: 1) conventional pseudo resistor (PR) [1], 2) switched-capacitor resistor (SCR) [2], 3) duty-cycled resistor (DCR) [3], and 4) tunable PR [4]–[6]. By connecting two back-to-back transistors operating in subthreshold region, conventional PR easily realizes the resistance with hundreds of GΩ, but its value varies with PVT over several orders of magnitude. On the contrary, DCR is less sensitive to PVT because its resistance mainly depends on the duty cycle of the clock. However, the maximal achievable resistance of DCR is limited to dozens of GΩ due to the parasitic capacitor. Also, DCR needs an anti-alias filter [2] to avoid noise increasing. A similar dilemma occurring in SCR, although [3] utilizes an SC circuit to attain hundreds-of-GΩ resistance to make the resistor insusceptible to PVT, nonetheless, noise aliasing is a problematic issue to circuit performance in like manner. Compared to DCR and SCR, the tunable PRs proposed in [4]–[6] circumvent noise aliasing due to continuous-time operation. However, to realize a resistor with hundreds of GO, a few picoamperes (pA) bias current $(mathrm{I}_{text{BIAS}})$ are required to generate very low VGS in circuit implementation. It is no doubt that a large deviation of resistance of PR will appear due to leakage current. Moreover, to realize the finely tuning of PR in the vicinity of hundreds-of-GΩ resistance, a few picoamperes (pA) bias current with 1 pA adjustment precision may be required, thus, the accuracy of tunable PR is further worsened.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132829540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cryogenic CMOS for Qubit Control and Readout 用于量子比特控制和读出的低温CMOS

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772841

S. Pellerano, Sushil Subramanian, Jong-Seok Park, B. Patra, T. Mladenov, X. Xue, L. Vandersypen, M. Babaie, E. Charbon, F. Sebastiano

引用次数: 9

Piezoelectric-Based Power Conversion: Recent Progress, Opportunities, and Challenges 基于压电的功率转换:最新进展、机遇和挑战

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772801

J. D. Boles, J. J. Piel, Ng Elaine, Joseph E. Bonavia, J. Lang, D. Perreault

{"title":"Piezoelectric-Based Power Conversion: Recent Progress, Opportunities, and Challenges","authors":"J. D. Boles, J. J. Piel, Ng Elaine, Joseph E. Bonavia, J. Lang, D. Perreault","doi":"10.1109/CICC53496.2022.9772801","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772801","url":null,"abstract":"Pursuits of miniaturization, greater performance, and lower cost for power electronics necessitate advancement of power passive component technologies. While wide-bandgap semiconductor devices and advanced control techniques have enabled substantial size and performance improvements, miniaturizing power electronics remains bottlenecked by the passive components dominating their sizes, particularly magnetics (i.e., inductors and transformers). Magnetic components pose fundamental power handling and efficiency challenges at small scales, amounting to lower power densities at low volume [1]–[3]. On the other hand, switched capacitor converters have achieved record-breaking power densities and efficiencies, but these architectures still require magnetics for efficient voltage regulation. While several miniaturization strategies have been developed despite the limitations of magnetics (e.g., higher switching frequencies, more sophisticated circuit topologies and operating techniques, and improved magnetic designs), they ultimately still face the same scaling impediments. This motivates investigation into alternative passive component technologies for power conversion that can provide the same high-level functionalities as magnetics but with superior scalability to small sizes.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132024076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation 一种用于多模式锁相神经刺激的16通道60µW神经同步处理器

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772806

Uisub Shin, Cong Ding, Laxmeesha Somappa, V. Woods, A. Widge, Mahsa Shoaran

{"title":"A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation","authors":"Uisub Shin, Cong Ding, Laxmeesha Somappa, V. Woods, A. Widge, Mahsa Shoaran","doi":"10.1109/CICC53496.2022.9772806","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772806","url":null,"abstract":"Measuring neural oscillatory synchrony facilitates our understanding of complex brain networks and the underlying pathological states. Altering the cross-regional synchrony-as a measure of brain network connectivity-via phase-locked deep brain stimulation (DBS) could provide a new therapeutic solution for various neurological [1] and psychiatric disorders [2]. This feature is missing in current neuromodulation devices and requires an accurate, energy-efficient computation of oscillatory phase and cross-regional synchrony on chip. The conventional iterative vector processing approach via CORDIC [3] can accurately extract the instantaneous phase and phase locking value (PLV) at the cost of high power consumption (400µW). As a result, it cannot be applied to large-scale (>100-CH) neuronal networks. Moreover, the latency in the pipelined CORDIC processor may hinder timely phase-locked stimulation in the absence of an excessively high clock speed. Alternatively, the PLV extractors in [4], [5] utilized simple approximation algorithms such as 1-bit quantization and local minima detection. These methods, albeit efficient, compromise PLV accuracy and cannot extract the instantaneous phase of neuronal signals. To provide an efficient, flexible, and accurate phase-locked DBS platform, this paper integrates a 16-channel low-noise AFE, an energy-efficient multi-mode phase synchrony processor, and a 4-channel neurostimulator that is locked to specific neuronal oscillatory phases (i.e., fixed or random phase, PLV or PAC). An amplitude-locked control can be further enabled through envelope and multi-band spectral energy extraction for common use cases such as epilepsy.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132113188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme 一个77μW 115db动态范围586fa灵敏度电流域连续变焦ADC，带脉宽调制电阻DAC和背景偏移补偿方案

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772794

Hao Zhang, Linxiao Shen, Shichuang Zhang, Heyi Li, Yihan Zhang, Z. Tan, R. Huang, Le Ye

引用次数: 2

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology 3nm栅极全能(GAA)设计-技术协同优化(DTCO)，用于后续技术PPA

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772784

T. Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, W. Rim, S. Baek, Sangyeop Baeck, Jonghoon Jung

引用次数: 2

T-PIM: A 2.21-to-161.08TOPS/W Processing-In-Memory Accelerator for End-to-End On-Device Training T-PIM:一个用于端到端设备上训练的2.21到161.08 tops /W内存处理加速器

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772808

Jaehoon Heo, Junsoo Kim, Won-Ok Han, Sukbin Lim, Joo-Young Kim

引用次数: 2

A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection 一种0.14nJ/b 200Mb/s闭环调制和边带能量检测的准平衡FSK收发器

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772812

Bowen Wang, Cong Ding, Yunzhao Nie, W. Rhee, Zhihua Wang

{"title":"A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection","authors":"Bowen Wang, Cong Ding, Yunzhao Nie, W. Rhee, Zhihua Wang","doi":"10.1109/CICC53496.2022.9772812","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772812","url":null,"abstract":"As the demand of high-speed communication is growing for mobile connectivity, the design of a low-power high-data-rate wireless transceiver is essential. Even though the binary FSK (BFSK) modulation is a popular choice for low-power transceiver systems [1]–[5], it has difficulty in achieving a high data rate unless an open-loop oscillator or an injection-pulling oscillator [6] is employed. The direct modulation of the VCO with an open-loop method or within a narrowband PLL suffers from the pulling effect. A closed-loop modulation based on the PLL is challenging for the high data rate due to a limited loop bandwidth or a delay mismatch in the case of the two-point modulation. Moreover, the closed-loop BFSK modulation suffers from a data-pattern-dependency problem when a wideband PLL is considered. The binary frequency-domain OOK (BFOOK) modulation method provides a way of achieving a fully-balanced FSK modulation [7]–[8], so that a wideband PLL can be designed to minimize the VCO pulling effect. The BFOOK modulation, however, occupies twice as much bandwidth as the conventional BFSK modulation. In this work, we propose a quasi-balanced FSK (QB-FSK) modulation to achieve enhanced bandwidth efficiency, while having negligible data-pattern dependency. Based on the proposed modulation method, we present a sub-6GHz FSK transceiver that achieves the highest data rate with the PLL-based modulation.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114279430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Phase-Modulation Phase-Shifting Phased-Array Transmitter with 10-Bit Fast-Locking Phase Self-Calibration and 0/2.5/6/12dB Power Back-Offs Efficiency Enhancement 具有10位快速锁相自校准和0/2.5/6/12dB功率回退效率增强的调相移相控阵发射机

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772731

Jie Zhou, H. Qian, Bingzheng Yang, Yiyang Shu, Xun Luo

{"title":"A Phase-Modulation Phase-Shifting Phased-Array Transmitter with 10-Bit Fast-Locking Phase Self-Calibration and 0/2.5/6/12dB Power Back-Offs Efficiency Enhancement","authors":"Jie Zhou, H. Qian, Bingzheng Yang, Yiyang Shu, Xun Luo","doi":"10.1109/CICC53496.2022.9772731","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772731","url":null,"abstract":"Increasing demands on high-data capacity accelerate developments of phased-array systems with beam steering for modern wireless applications (e.g., 5G, WiFi) [1]. RF phase-shifting phased-array transmitter (TX) (Fig. 1-top-left) offers an architecture with shared mixers in system implementation. However, since the phase shifters (PSs) are placed in the RF signal path, the non-ideality of PSs, such as gain variation and implicit nonlinearity, cannot be ignored. LO phase-shifting phased-array TX (Fig. 1-top-center) places the PSs in LO signal path with increased number of mixers, which can decease the deterioration from PSs. Nevertheless, both in RF and LO phase-shifting phased-array TXs, an extra modulator to generate the modulated IF signal from baseband is necessary. Meanwhile, additional phase calibration in such phased-array TXs is usually needed. Recently, phase-modulation (PM) phase-shifting digital polar phased-array TX (Fig. 1-top-right) is proposed to achieve direct-modulation and beam-steering, simultaneously [2]. Besides, it can decease the impact from PSs' non-ideality, due to the constant envelope of PM signals. However, the digital pre-distortion (DPD) for modulation and phase-shifting is still required.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117223667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Wireless Frequency-Division Multiplexed 3D Magnetic Localization for Low Power Sub-mm Precision Capsule Endoscopy 低功率亚毫米级精密胶囊内窥镜的无线频分复用三维磁定位

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772802

Michella Rustom, Constantine Sideris

引用次数: 4