3nm栅极全能(GAA)设计-技术协同优化(DTCO)，用于后续技术PPA

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI:10.1109/CICC53496.2022.9772784

T. Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, W. Rim, S. Baek, Sangyeop Baeck, Jonghoon Jung

{"title":"3nm栅极全能(GAA)设计-技术协同优化(DTCO)，用于后续技术PPA","authors":"T. Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, W. Rim, S. Baek, Sangyeop Baeck, Jonghoon Jung","doi":"10.1109/CICC53496.2022.9772784","DOIUrl":null,"url":null,"abstract":"3nm Gate-All-Around (GAA) technology is introduced to suggest the future of logic transistor with performance, power, and area (PPA) benefit. However, as with the recent advanced technologies, GAA technology also faces the potential challenges to overcome for the optimum PPA. Therefore, Design-Technology Co-Optimization (DTCO) has become more important than ever to maximize technology-to-design benefits of GAA. In this paper, the motivation of DTCO is presented by showing the successful design examples in advanced technologies. Then, the design techniques of standard cell and SRAM compiler are proposed based on DTCO to maximize the benefit of 3nm GAA technology.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"14 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology\",\"authors\":\"T. Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, W. Rim, S. Baek, Sangyeop Baeck, Jonghoon Jung\",\"doi\":\"10.1109/CICC53496.2022.9772784\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"3nm Gate-All-Around (GAA) technology is introduced to suggest the future of logic transistor with performance, power, and area (PPA) benefit. However, as with the recent advanced technologies, GAA technology also faces the potential challenges to overcome for the optimum PPA. Therefore, Design-Technology Co-Optimization (DTCO) has become more important than ever to maximize technology-to-design benefits of GAA. In this paper, the motivation of DTCO is presented by showing the successful design examples in advanced technologies. Then, the design techniques of standard cell and SRAM compiler are proposed based on DTCO to maximize the benefit of 3nm GAA technology.\",\"PeriodicalId\":415990,\"journal\":{\"name\":\"2022 IEEE Custom Integrated Circuits Conference (CICC)\",\"volume\":\"14 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Custom Integrated Circuits Conference (CICC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC53496.2022.9772784\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC53496.2022.9772784","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

介绍了3nm栅极全能(GAA)技术，提出了具有性能、功率和面积(PPA)优势的逻辑晶体管的未来。然而，与最近的先进技术一样，GAA技术也面临着实现最佳PPA的潜在挑战。因此，设计-技术协同优化(DTCO)比以往任何时候都更加重要，以最大限度地提高GAA的技术-设计效益。本文通过介绍先进技术的成功设计实例，阐述了DTCO的设计动机。然后，提出了基于DTCO的标准单元和SRAM编译器的设计技术，以最大限度地发挥3nm GAA技术的优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology

3nm Gate-All-Around (GAA) technology is introduced to suggest the future of logic transistor with performance, power, and area (PPA) benefit. However, as with the recent advanced technologies, GAA technology also faces the potential challenges to overcome for the optimum PPA. Therefore, Design-Technology Co-Optimization (DTCO) has become more important than ever to maximize technology-to-design benefits of GAA. In this paper, the motivation of DTCO is presented by showing the successful design examples in advanced technologies. Then, the design techniques of standard cell and SRAM compiler are proposed based on DTCO to maximize the benefit of 3nm GAA technology.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2022 IEEE Custom Integrated Circuits Conference (CICC)

自引率

0.00%

发文量