2022 IEEE Custom Integrated Circuits Conference (CICC)最新文献_第3页

A 1-to-4GHz Multi-Mode Digital Transmitter in 40nm CMOS Supporting 200MHz 1024-QAM OFDM signals with more than 23dBm/66% Peak Power/Drain Efficiency 1- 4ghz多模数字发射机，40nm CMOS，支持200MHz 1024-QAM OFDM信号，峰值功率/漏极效率超过23dBm/66%

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772797

M. Beikmirza, Yiyu Shen, L. D. Vreede, M. Alavi

{"title":"A 1-to-4GHz Multi-Mode Digital Transmitter in 40nm CMOS Supporting 200MHz 1024-QAM OFDM signals with more than 23dBm/66% Peak Power/Drain Efficiency","authors":"M. Beikmirza, Yiyu Shen, L. D. Vreede, M. Alavi","doi":"10.1109/CICC53496.2022.9772797","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772797","url":null,"abstract":"To support wideband complex modulated signals and comply with the stringent requirements of modern communication standards in an energy-efficient manner, recently, digital transmitters (DTXs) have been explored to fully benefit from the high-speed switching and integration capabilities of nanoscale CMOS technologies [1]–[5]. These DTXs are primarily exploiting a polar or Cartesian architecture. In a polar DTX [1], [2], two eigenvectors of amplitude (p) and phase $(phi)$ are generated from the in-phase (I) and quadrature (Q) baseband signals using non-linear coordinate rotation transformations (i.e., CORDIC). Provided that $rho$ is constant, the achievable drain efficiency (DE) is constant (Fig. 1 top). However, polar $text{DTXs}$ cannot manage large modulation bandwidth due to their non-linear $mathrm{I}/mathrm{Q}$ to $rho/phi$ conversion. Moreover, their phase and amplitude paths must recombine at the output stage without any delay mismatch to maintain linear operation. In contrast, Cartesian DTX variants can handle signals with large modulation bandwidth [3]. Nevertheless, their DE is lower than their polar counterparts owing to the linear combination of orthogonal I/Q vectors, yielding a 3-dB worst-case output power loss at the orthogonal (I/Q) axes. Alternatively, a multi-phase operation can be utilized that compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with 45° relative phase difference and magnitudes of $mathrm{I}_{text{MP}}=mathrm{I}-mathrm{Q}$, QMP $=sqrt{2}mathrm{Q}$ [4]. This architecture inherits the advantages of the cartesian DTX, such as wideband operation, symmetrical, and synchronized $mathrm{I} /mathrm{Q}$ paths along with a DE behavior that imitates the polar case. This paper presents a multi-mode DTX that uses both Cartesian and multi-phase operation modes to target applications requiring large modulation bandwidth, decent spectral purity and average efficiency.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134577059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An Up to 10MHz 6.8% Minimum Duty Ratio GaN Driver with Dual-MOS-Switches Bootstrap and Adaptive Short-Pulse Based High-CMTI Level Shifter Achieving 6.05% Efficiency Improvement 具有双mos开关自引导和基于自适应短脉冲的高cmti电平移位器的高达10MHz 6.8%最小占空比GaN驱动器实现了6.05%的效率提升

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772869

Xin Ming, Zhikang Lin, Tian-yi Sun, Yao Qin, Yuan-Yuan Liu, Chun-wang Zhuang, Zhaoji Li, Bo Zhang

引用次数: 3

High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range 面向高动态范围的高速数模转换器设计

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772809

Shiyu Su, M. Chen

引用次数: 0

A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing 一个10b 700MS/s单通道1b/周期SAR ADC，采用单调特定反馈SAR逻辑，具有功率延迟优化的非平衡N/P-MOS尺寸

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772843

Mingqiang Guo, Sai-Weng Sin, Liang Qi, Gang Xiao, R. Martins

引用次数: 3

A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET 22nm FinFET中带速度增强自启动开关的38GS/s 7b时脉交错流水线sar ADC

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772785

Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, II-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, S. Hoyos, S. Palermo

{"title":"A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET","authors":"Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, II-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, S. Hoyos, S. Palermo","doi":"10.1109/CICC53496.2022.9772785","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772785","url":null,"abstract":"High-speed time-interleaved ADCs are becoming more common in wireline receiver front-ends due to the enabling of subsequent digital processing for equalization and easier support of higher-order modulation schemes [1]. As technology nodes scale, ADCs based on the digital-intensive SAR architecture are more pervasive. However, implementations with the most common SAR algorithm that has sequential single-bit conversion cycles can result in large time-interleaving factors. Also, the sampling of wideband analog signals associated with higher data rates is difficult for conventional bootstrapped switch (BS) T/H circuits that have not adequately scaled in performance. One reason for this is that the low-duty-cycle sampling clocks, which are utilized for avoiding sampling crosstalk between time-interleaved sub-ADCs, shorten the tracking time and requires improvements in T/H circuit startup time. This motivates the use of simple NMOS switches in high-speed ADCs [2], [3]. However, this can negatively impact the high-speed linearity and ADC front-end bandwidth and also require higher supply voltages. This paper presents an ADC that utilizes both a high-bandwidth interleaver architecture based on a speed-enhanced bootstrapped switch and a pipelined-SAR unit ADC with output level shifting (OLS) settling [4] to enable low-power high-speed operation. At 38GS/s, the 7b ADC achieves 41.9fJ/conv.-step at low input frequencies, 64.1fJ/conv.-step at Nyquist, and has 20GHz 3dB bandwidth.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128629604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes 基于共封装光电二极管的16nm CMOS 4-PAM线性TIA灵敏度为112gb /s -8.2 dBm

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772827

Dhruv Rajendra Patel, A. Sharif-Bakhtiar, A. C. Carusone

引用次数: 9

22-30GHz Quadrature Hybrid SCPA with LO Leakage Self-Suppression and Distributed Parasitic-Cancelling Sub-PA Array for Linearity and Efficiency Enhancement 基于低漏自抑制和分布式寄生对消Sub-PA阵列的22-30GHz正交混合SCPA线性度和效率提高

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772777

Bingzheng Yang, H. Qian, Yiyang Shu, Jie Zhou, Xun Luo

{"title":"22-30GHz Quadrature Hybrid SCPA with LO Leakage Self-Suppression and Distributed Parasitic-Cancelling Sub-PA Array for Linearity and Efficiency Enhancement","authors":"Bingzheng Yang, H. Qian, Yiyang Shu, Jie Zhou, Xun Luo","doi":"10.1109/CICC53496.2022.9772777","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772777","url":null,"abstract":"To meet the demands of multi-Gb/s data-rate wireless transmission such as millimeter wave (mmW) 5G wireless, there is a growing requirement of mmW transmitters (TXs) with high output power, high efficiency, and high data-rate [1], [2]. The digital power amplifier (DPA) shows the merits of high system efficiency, high integration with baseband, and low cost compared with analog PAs [3], which is potential for mmW 5G TX. However, the increasing parasitic of transistor at mmW limits switching speed, which leads to efficiency degradation [4]–[6]. Meanwhile, the routing parasitics deteriorate the output power and efficiency of mmW DPA [5]. DPA usually suffers from relatively large LO leakage at mmW, which decreases the dynamic range and introduces linearity issue. To overcome these challenges, a 2×9-bit quadrature hybrid switched-capacitor PA (SCPA) with LO leakage self-suppression and distributed parasitic-cancelling sub-PA array is proposed, which achieves saturated Pout of 24.03dBm with peak system efficiency (SE) of 31.5% at 24GHz.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127102962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

[Copyright notice] (版权)

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/cicc53496.2022.9772807

引用次数: 0

IC and Array Technologies for 100-300GHz Wireless 100-300GHz无线集成电路和阵列技术

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772844

M. Rodwell, Ahmed S. H. Ahmed, M. Seo, Utku Soylu, A. Alizadeh, Navid Hosseinzadeh

引用次数: 10

Comprehending In-memory Computing Trends via Proper Benchmarking 通过适当的基准测试来理解内存计算趋势

2022 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2022-04-01 DOI: 10.1109/CICC53496.2022.9772817

Naresh R Shanbhag, Saion K. Roy

{"title":"Comprehending In-memory Computing Trends via Proper Benchmarking","authors":"Naresh R Shanbhag, Saion K. Roy","doi":"10.1109/CICC53496.2022.9772817","DOIUrl":"https://doi.org/10.1109/CICC53496.2022.9772817","url":null,"abstract":"Since its inception in 2014 [1], the modern version of in-memory computing (IMC) has become an active area of research in integrated circuit design globally for realizing artificial intelligence and machine learning workloads. Since 2018, > 40 IMC-related papers have been published in top circuit design conferences demonstrating significant reductions (>20X) in energy over their digital counterparts especially at the bank-level. Today, bank-level IMC designs have matured but it is not clear what the limiting factors are. This lack of clarity is due to multiple reasons including: 1) the conceptual complexity of IMCs due to its full-stack (devices-to-systems) nature, 2) the presence of a fundamental energy-efficiency vs. compute SNR trade-off due to its analog computations, and 3) the statistical nature of machine learning workloads. The absence of a rigorous benchmarking methodology for IMCs - a problem facing machine learning ICs in general [2] - further obfuscates the underlying trade-offs. As a result, it has become difficult to evaluate the novelty of IMC-related ideas being proposed and therefore gauge the true progress in this exciting field.","PeriodicalId":415990,"journal":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132421412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7