A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes

Abstract

Low-cost optical receivers (RX) operating at 100+ Gb/s 4-PAM with low power are in high demand to support 400GBASE-DR4/FR4 links in data centers. Existing pluggable solutions generally realize the RX front-end in BiCMOS. However, a more integrated solution, with the RX front-ends integrated onto a CMOS host IC and co-packaged alongside the photodiodes (PDs), offers the potential for smaller size, lower cost, and lower power [1], [2]. This work demonstrates a 112 Gb/s 4-PAM linear TIA in CMOS flip-chip co-packaged with commercial PDs and different PD-to-RX interconnect lengths (Fig. 1a).