Tim Schumacher, Markus Stadelmayer, Thomas Faseth, H. Pretl
{"title":"A Review of Ultra-Low-Power and Low-Cost Transceiver Design","authors":"Tim Schumacher, Markus Stadelmayer, Thomas Faseth, H. Pretl","doi":"10.1109/AUSTROCHIP.2017.15","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.15","url":null,"abstract":"This paper reviews trends for ultra-low-power wireless transceiver system and integrated circuit design under the perspective of using cost-effective CMOS technology nodes. These efficient transceiver structures typically find application in devices such as fitness monitors and other wearable healthcare devices, Internet of Things (IoT) devices and generic sensor nodes. A brief overview of State-of-the-Art (SoA) architectures, techniques, and performance metrics of ultra-low-power transmitter and receiver structures is presented. The often conflicting demands of communication range, data rate, reliability, and energy consumption are examined and a typical case study of a transceiver for medical sensor nodes is presented.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"454 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132608927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Measurement and Comparison of Several Pass Transistor Logic Styles in a 350nm Technology","authors":"Andreas Rauchenecker, T. Ostermann","doi":"10.1109/AUSTROCHIP.2017.18","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.18","url":null,"abstract":"The performance of digital circuits can be improved by more efficient implementation. For certain circuits this can be done by using pass transistor logic. This paper compares pass transistor logic styles with the standard CMOS logic style. It will be shown that pass transistor logic is able to outperform the standard approach, not only by simulation but by measurements in silicon. Measurements have been executed over a temperature range from -40°C to 80°C and a supply voltage range from 2.7V to 3.6V. Simulation models are also verified through a comparison of the real measured data with simulation data.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115755891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Benjamin Willsch, Kai-Uwe Müller, Qi Zhang, J. Hauser, S. Dreiner, Alexander Stanitzki, H. Kappert, R. Kokozinski, H. Vogt
{"title":"Implementation of an Integrated Differential Readout Circuit for Transistor-Based Physically Unclonable Functions","authors":"Benjamin Willsch, Kai-Uwe Müller, Qi Zhang, J. Hauser, S. Dreiner, Alexander Stanitzki, H. Kappert, R. Kokozinski, H. Vogt","doi":"10.1109/AUSTROCHIP.2017.14","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.14","url":null,"abstract":"Physically Unclonable Functions (PUFs) offer enticing possibilities to incorporate hardware-based security on semiconductor device level. In order to make efficient use of PUF functionality in lightweight cryptographic applications, a low-overhead implementation in terms of chip area and power consumption is required. In this paper a fully differential readout circuit is proposed that allows the generation of multiple bits from selected pairs of PUF-elements. The IC-design and working principle are explained on basis of a critically-sized nMOS transistor array serving as a PUF-primitive. First results obtained from circuit simulations and wafer-level measurements of 30 PUF-instances fabricated in a 0.35µm CMOS technology are presented. Evaluation of the intra- and inter-Hamming distance with average values of 9.42% and 49.46%, respectively, shows that device identification based on the extracted keys is feasible. In order to increase the number of unique keys obtainable for each PUF-instance layout improvements in form of additional row select connections are proposed.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132268219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}