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Using Python Tools to Assist Mixed-Signal ASIC Design and Verification Methodologies 使用Python工具辅助混合信号ASIC设计和验证方法
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.17
Evangelos Logaras, Andreas Weitzer
{"title":"Using Python Tools to Assist Mixed-Signal ASIC Design and Verification Methodologies","authors":"Evangelos Logaras, Andreas Weitzer","doi":"10.1109/AUSTROCHIP.2017.17","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.17","url":null,"abstract":"We present a set of tools for digital design, integration and verification of mixed-signal Application Specific Integrated Circuits (ASIC) developed within our design team. We have chosen Python for the development of the tools. By drawing on Python's features we have developed tools targeting many steps required across a design flow: a) Complex digital blocks are auto-generated, where Python generates, according to input files thousands of Register Transfer Level (RTL) lines of code. b) Using the tool a full RTL design hierarchy can be parsed and using the extracted information a number of RTL and report files are generated, providing useful information for RTL integration activities. c) Simulation related files and especially IP-XACT models can be used in a Universal Verification Methodology (UVM) simulation environment to model digital blocks and accelerate verification activities. d) Back-end tools support to define power constraints and analyze timing reports.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"37 7-8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120892626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of a Charge-Controlled Stimulation Method in a Monolithic Integrated CMOS-Chip for Excitation of Retinal Neuron Cells 在单片集成cmos芯片上实现电荷控制刺激视网膜神经元细胞
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.9
R. Viga, P. Walter, R. Kokozinski, A. Grabmaier
{"title":"Implementation of a Charge-Controlled Stimulation Method in a Monolithic Integrated CMOS-Chip for Excitation of Retinal Neuron Cells","authors":"R. Viga, P. Walter, R. Kokozinski, A. Grabmaier","doi":"10.1109/AUSTROCHIP.2017.9","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.9","url":null,"abstract":"In this work, the implementation of the chargecontrolled method in a CMOS chip is presented. The idea of the method is that the transferred total charge quantity is composed of a number of packets which are intended to stimulate the cells of the retina electrically. In addition, it will be compared with already established methods. The influence of electrode interfaces on the process is investigated in the analytical description as well. Furthermore, options for the implementation in an integrated circuit are presented, in which a feedback is used to control the transferred charge amount per clock. Finally, a system concept for simultaneous bidirectional communication between retinal cells and the electronics is presented. Read-out capabilities for increasing the stimulation safety are shown.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"125 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128740000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of Semiconductor Process Variations by Means of Hierarchical Median Polish 用分层中值抛光方法分析半导体工艺变化
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.19
Benjamin Willsch, J. Hauser, S. Dreiner, A. Goehlich, H. Kappert, H. Vogt
{"title":"Analysis of Semiconductor Process Variations by Means of Hierarchical Median Polish","authors":"Benjamin Willsch, J. Hauser, S. Dreiner, A. Goehlich, H. Kappert, H. Vogt","doi":"10.1109/AUSTROCHIP.2017.19","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.19","url":null,"abstract":"The understanding and controlling of semiconductor process variation is crucial to the performance, functionality and reliability of modern ICs. Due to the complex fabrication process involving hundreds of processing steps, the analysis of the sources of variability is a non-trivial task. In this paper, a novel, simple-to-implement procedure named Hierarchical Median Polish is proposed. The method is designed to decompose the spatial variation of device properties obtained from waferlevel measurements. The decomposition yields non-parametric estimates of the systematic and random variation components on different spatial scales such as wafer-, die- and intra-die level. The practicability of the approach is demonstrated by applying the procedure to wafer-level measurement data of 12100 poly resistors fabricated in a standard CMOS technology.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129937004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
DC/AC Compact Modeling of TFETs for Circuit Simulation of Logic Cells Based on an Analytical Physics-Based Framework 基于分析物理框架的逻辑单元电路仿真tfet的DC/AC紧凑建模
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.10
F. Horst, A. Farokhnejad, M. Graef, Fabian Hosenfeld, G. V. Luong, Chang Liu, Qing-Tai Zhao, F. Lime, B. Iñíguez, A. Kloes
{"title":"DC/AC Compact Modeling of TFETs for Circuit Simulation of Logic Cells Based on an Analytical Physics-Based Framework","authors":"F. Horst, A. Farokhnejad, M. Graef, Fabian Hosenfeld, G. V. Luong, Chang Liu, Qing-Tai Zhao, F. Lime, B. Iñíguez, A. Kloes","doi":"10.1109/AUSTROCHIP.2017.10","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.10","url":null,"abstract":"This paper presents a DC/AC compact model for double-gate (DG) tunnel field-effect transistors (TFET) which is based on a unified analytical modeling framework. The closed-form model shows a good agreement with both, TCAD simulations and measurements on test structures. A Verilog-A implementation allows for a quick performance evaluation of the DC performance of logic cells. Results of a complementary TFET inverter are in good agreement to measurements. Simulations of an 8T SRAM cell clearly show the critical influence of the ambipolar behavior and leakage current on the performance. The fundamental analytical modeling framework provides deeper physical insight while considering additional effects as trap-assisted tunneling (TAT), junction profile steepness and hetero structures.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"49 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123433461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Receiver Chip in 0.6µm BiCMOS with AGC and LVDS Output Driver 接收芯片采用0.6µm BiCMOS，带AGC和LVDS输出驱动器
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.16
B. Goll, R. Swoboda, H. Zimmermann
{"title":"Receiver Chip in 0.6µm BiCMOS with AGC and LVDS Output Driver","authors":"B. Goll, R. Swoboda, H. Zimmermann","doi":"10.1109/AUSTROCHIP.2017.16","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.16","url":null,"abstract":"An integrated receiver chip for external photodiodes (PDs) is presented in 0.6µm BiCMOS technology with 3.3V supply voltage. It consists of an internal Automatic Gain Control (AGC), which simultaneously compensates the frequency characteristics, an internal charge pump, which delivers optionally 5V to external PDs, a detector to show whether data is received and a 50Ω differential output driver for LVDS (low voltage differential signaling) logical standard. The chip was tested electrically without PD as well as with the commercially available PIN PDs S5973 (Hamamatsu) and PS0.25-5 SMD (Silicon Sensor International AG). The power consumption amounts to 113mW and a maximum data rate of 3.2Gb/s was measured electrically, where a current sensitivity (BER=10E-9) of 21µA mean input current was achieved. At 1.25Gb/s a current sensitivity of 4.1µA was measured. With external PDs bonded to the receiver the optical sensitivity was -14.7dBm (1.25Gb/s, λ=780nm) for S5973 and -20.3dBm (1Gb/s, λ=850nm) mean optical power at the input for PS0.25-5 SMD. With these results the receiver chip might be a low-cost alternative for plastic optical fiber (POF) receivers, optical LAN, data comm receivers or for Optical Wireless Communication (OWC) receivers. To achieve higher sensitivities an external Avalanche Photodiode (APD) could be connected easily to the receiver chip instead of PIN PDs.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116824723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Survey on Integrated High-Power Low-Emission Output Stages for Drivers of Low-Frequency Resonant Loads 用于低频谐振负载驱动的集成大功率低排放输出级研究
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.20
H. Hackl, M. Auer, R. Erckert
{"title":"Survey on Integrated High-Power Low-Emission Output Stages for Drivers of Low-Frequency Resonant Loads","authors":"H. Hackl, M. Auer, R. Erckert","doi":"10.1109/AUSTROCHIP.2017.20","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.20","url":null,"abstract":"To drive low-frequency resonant loads with high output power and low emission, Class-AB push-pull stages are state of the art. But their theoretically superior emission performance is often sacrificed for efficiency. A differential Class-D concept is a promising alternative, because it can combine both excellent power efficiency and low missions. This work is a survey on the main sources of distortions for both amplifier topologies with basic considerations to internal power losses and efficiency. The investigations are based on simple circuits and compared to measurement results of two integrated circuits.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121696380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Circuit Technique for Blocker-Induced Modulated Spur Cancellation in 4G LTE Carrier Aggregation Transceivers 4G LTE载波聚合收发器中阻塞诱导的调制杂散抵消电路技术
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.21
Silvester Sadjina, Dufrene Krzysztof, R. S. Kanumalli, M. Huemer, H. Pretl
{"title":"A Circuit Technique for Blocker-Induced Modulated Spur Cancellation in 4G LTE Carrier Aggregation Transceivers","authors":"Silvester Sadjina, Dufrene Krzysztof, R. S. Kanumalli, M. Huemer, H. Pretl","doi":"10.1109/AUSTROCHIP.2017.21","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.21","url":null,"abstract":"In this paper, we propose a novel mixed-signal cancellation circuit for LTE carrier aggregation receivers targeting modulated spur interference. This circuit senses interference via an auxiliary analog path, and generates a reference signal for the adaptive digital cancellation. To evaluate the performance of the proposed technique, a demonstrator, realized in 28 nm LP CMOS, is shown with a cancellation of over 20dB and low impact on the main path while consuming 14.3 mW. Measurement results show that the receiver's noise figure is restored to a value within 0.1 dB of the reference value.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115439571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
CMOS Open-Loop Local Quadrature Phase Generator for 5G Applications 用于5G应用的CMOS开环局部正交相位发生器
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.11
Michael Kalcher, Daniel Gruber
{"title":"CMOS Open-Loop Local Quadrature Phase Generator for 5G Applications","authors":"Michael Kalcher, Daniel Gruber","doi":"10.1109/AUSTROCHIP.2017.11","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.11","url":null,"abstract":"An open-loop feedback-less CMOS quadrature (I/Q) local oscillator (LO) signal generator is presented. The circuit generates differential 90° shifted LO outputs from a differential input LO at the very same frequency. The phase accuracy of the implemented circuit relies on the matching of two delays and linear phase interpolation. The presented circuit is designed in a 28 nm bulk-CMOS technology implemented without any passive components covering an operating frequency range from 5 GHz up to 6 GHz. Simulation results of the designed I/Q generator show a worst case phase noise performance of –151.3 dBc/Hz at 100 MHz offset with a worst case power consumption of only 3.4 mW from a 0.95 V supply.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133152160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A FPGA-Based Demonstrator for Safety-Critical Applications 基于fpga的安全关键应用演示器
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.13
Christian Fibich, Peter Röessler, Stefan Tauner, Martin Matschnig, Herbert Taucher
{"title":"A FPGA-Based Demonstrator for Safety-Critical Applications","authors":"Christian Fibich, Peter Röessler, Stefan Tauner, Martin Matschnig, Herbert Taucher","doi":"10.1109/AUSTROCHIP.2017.13","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.13","url":null,"abstract":"This work presents a demonstrator for safety-critical applications based on a low-cost FPGA platform. The main goal of the demonstrator is to show the features and benefits of a fault-injection tool for FPGAs called FIJI (Fault Injection Instrumenter) that was developed by the authors of this paper. Besides, the demonstrator should illustrate typical sources of hardware/software faults as well as approaches and methods for fault-tolerant design that are commonly applied to modern electronic based systems. Both details of the demonstrator's design as well as implementation results including the overhead on resources caused by the proposed fault-injection logic are presented. The demonstrator is portable to FPGA families of different FPGA vendors and can be implemented by using freeware/open-source design tools. Finally, it is planned that all design data of the demonstrator (including source code and documentation) will be available under an open-source license.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122539678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Compact, Low Power and High Sensitivity E-Band Frequency Divider SiGe HBT MMIC 一个紧凑，低功耗和高灵敏度的e波段分频SiGe HBT MMIC
2017 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2017-10-01 DOI: 10.1109/AUSTROCHIP.2017.12
A. Dyskin, P. Harati, I. Kallfass
{"title":"A Compact, Low Power and High Sensitivity E-Band Frequency Divider SiGe HBT MMIC","authors":"A. Dyskin, P. Harati, I. Kallfass","doi":"10.1109/AUSTROCHIP.2017.12","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2017.12","url":null,"abstract":"A compact inductorless E-band static frequency divider with the division ratio of 8 is reported in this paper. It has a sensitivity of -43 dBm at the self-oscillating frequency of 75.3 GHz and sports the sensitivity better than -14 dBm in a frequency range from 70 to 77 GHz. The divider consists of 3 emitter-coupled logic based dividers with the division ratio of 2. High frequency of operation and low power consumption are achieved by introducing a split-resistors load topology, improved by means of a critical interconnections optimization. With these circuit measures, the current consumption of the E-band divider-by-8 can be effectively reduced to 63 mA.","PeriodicalId":415804,"journal":{"name":"2017 Austrochip Workshop on Microelectronics (Austrochip)","volume":"68 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120992999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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