Using Python Tools to Assist Mixed-Signal ASIC Design and Verification Methodologies

We present a set of tools for digital design, integration and verification of mixed-signal Application Specific Integrated Circuits (ASIC) developed within our design team. We have chosen Python for the development of the tools. By drawing on Python's features we have developed tools targeting many steps required across a design flow: a) Complex digital blocks are auto-generated, where Python generates, according to input files thousands of Register Transfer Level (RTL) lines of code. b) Using the tool a full RTL design hierarchy can be parsed and using the extracted information a number of RTL and report files are generated, providing useful information for RTL integration activities. c) Simulation related files and especially IP-XACT models can be used in a Universal Verification Methodology (UVM) simulation environment to model digital blocks and accelerate verification activities. d) Back-end tools support to define power constraints and analyze timing reports.