Implementation of an Integrated Differential Readout Circuit for Transistor-Based Physically Unclonable Functions

Abstract

Physically Unclonable Functions (PUFs) offer enticing possibilities to incorporate hardware-based security on semiconductor device level. In order to make efficient use of PUF functionality in lightweight cryptographic applications, a low-overhead implementation in terms of chip area and power consumption is required. In this paper a fully differential readout circuit is proposed that allows the generation of multiple bits from selected pairs of PUF-elements. The IC-design and working principle are explained on basis of a critically-sized nMOS transistor array serving as a PUF-primitive. First results obtained from circuit simulations and wafer-level measurements of 30 PUF-instances fabricated in a 0.35µm CMOS technology are presented. Evaluation of the intra- and inter-Hamming distance with average values of 9.42% and 49.46%, respectively, shows that device identification based on the extracted keys is feasible. In order to increase the number of unique keys obtainable for each PUF-instance layout improvements in form of additional row select connections are proposed.