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A NEW APPROACH TO SECURE DATA AGGREGATION IN WIRELESS SENSOR NETWORKS  一种新的无线传感器网络数据聚合安全方法
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/03.01.01
V. Bindu, Dr. P. Senguttuvan
{"title":"A NEW APPROACH TO SECURE DATA AGGREGATION IN WIRELESS SENSOR NETWORKS ","authors":"V. Bindu, Dr. P. Senguttuvan","doi":"10.31838/ijccts/03.01.01","DOIUrl":"https://doi.org/10.31838/ijccts/03.01.01","url":null,"abstract":"However, primarily due to the severe constraints and secondarily due to the inherent increased costs in communications relative to that in processing, the WSNs follow in-network processing, wherein the emphasis is on on-thefly processing of the data packets before being communicated eventually to the base station [3]. The processing typically consists of the data aggregation operations like summarization, summation, averaging, finding the minimum/maximum of a set of sensed values. The eventual advantage of data aggregation is the overall reduction on the total number of packets transmitted to the base station resulting in conservation of energy and bandwidth. 2. REVIEW OF LITERATURE","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117080539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
6-bit, 180nm Digital to Analog Converter (DAC) Using Tanner EDA Tool for Low Power Applications  6位，180nm数模转换器(DAC)，采用Tanner EDA工具，用于低功耗应用
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/05.02.08
S.Surender K.Venkatachalam and V.Gowrishankar
{"title":"6-bit, 180nm Digital to Analog Converter (DAC) Using Tanner EDA Tool for Low Power Applications ","authors":"S.Surender K.Venkatachalam and V.Gowrishankar","doi":"10.31838/ijccts/05.02.08","DOIUrl":"https://doi.org/10.31838/ijccts/05.02.08","url":null,"abstract":"This paper describes a CMOS current-steering digital-to-analog converter with a full-swing output signal. In a Wireless system the quality of the communication link is main criteria, for great distance transmission it is necessary to convert analog signal into digital signal at input side, same as convert digital signal to analog signal at output side. In the Existing DAC, 6 Binary inputs to 63 thermometer-coded (unary) outputs will use 6-input NOR and NAND logic gate, and the timing delay of these gates are very different. As the clock rate rising, it will cause error decoding problems.so we propose the 6 to 63 thermometer decoder by 2 section decoding. There is two 3 to 7 thermometer decoder for column and row decoder. This scheme reduces the error decoding problems. A new scheme of the quaternary driver and an output current cell composed of both nMOS and pMOS.The nMOS operates from the power supply to the half of the supply. The pMOS operates independently from the half of the supply to the ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver that selects the optimized current cell. The circuit is simulated using 180nm Complementary Metal-oxide Semiconductor technology at a power supply voltage of 3.0 V on Tanner tool and the power consumption is about 17.8 mW. The proposed Current Steering Digital to Analog converter are schematic using Tanner S-EDIT and simulation of the proposed work is done using Tanner TEDIT. The waveform analysis is done using Tanner W-EDIT software","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130057378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SECURITY CONFIGURATION AND PERFORMANCE ANALYSIS OF FTP SERVER  FTP服务器的安全配置和性能分析
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/02.02.07
S. Singh, Jaipur
{"title":"SECURITY CONFIGURATION AND PERFORMANCE ANALYSIS OF FTP SERVER ","authors":"S. Singh, Jaipur","doi":"10.31838/ijccts/02.02.07","DOIUrl":"https://doi.org/10.31838/ijccts/02.02.07","url":null,"abstract":"File Transfer Protocol is used for transferring files to clients over networks using client-server architecture. FTP provides two mechanisms for file transfer; one is anonymous method and another one is password authentication mechanism. All the communication between client and server is without encryption means data is transferred in clear text whether it is password or ftp commands. There are some requirements which are considered important while file transfers and these are Authentication, Integrity and Confidentiality. For implementing security in file transfer protocol we use FTPS rather than FTP as it is more secure. As FTPS uses some encryption mechanisms, it adds some extra process which effects the performance. FTP and FTPS are configured according to the security requirements for file transfer. Adding some extra process overhead in FTPS like encryption, it affects the performance. This research paper compares both FTPS and FTP on Linux and Windows server.","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130304411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis on FPGA Designs of Parallel High Performance Multipliers  并行高性能乘法器的FPGA设计分析
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/02.01.03
R. Saveetha
{"title":"Analysis on FPGA Designs of Parallel High Performance Multipliers ","authors":"R. Saveetha","doi":"10.31838/ijccts/02.01.03","DOIUrl":"https://doi.org/10.31838/ijccts/02.01.03","url":null,"abstract":"For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. In this paper, optimized high performance parallel GF(2 233 ) multipliers for an FPGA realization were designed and the time and area complexities were analyzed. One of the multipliers uses a new hybrid structure to implement the Karatsuba algorithm. For increasing performance, we make excessive use of pipelining and efficient control techniques and use a modern state-of-the-art FPGA technology. As a result we have, to our knowledge, the first hardware realization of sub quadratic arithmetic and currently the fastest and most efficient implementation of 233 bit finite field multipliers.","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"58 7-8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130584624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Survey of load balancing routing protocols in MANET  MANET中负载均衡路由协议综述
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/03.02.02
V.Kalaiyarasi, Dr.M.Tamilarasi Pg student
{"title":"Survey of load balancing routing protocols in MANET ","authors":"V.Kalaiyarasi, Dr.M.Tamilarasi Pg student","doi":"10.31838/ijccts/03.02.02","DOIUrl":"https://doi.org/10.31838/ijccts/03.02.02","url":null,"abstract":"A mobile ad hoc network is a group of wireless mobile hosts forming a temporary network without the aid of any stand-alone infrastructure administration. Mobile Ad-hoc networks are self organizing and self-configuring multihop wireless networks where the network structure changed dynamically. This is mainly due to the mobility of the nodes. Nodes in these networks cooperating in a gracious manner to engaging themselves in multihop forwarding. The nodes in the network not only act as hosts but also act as routers that route data to/from other nodes in network. MANETs requires an efficient routing protocol that provides the quality of service (QoS) mechanism. Routing protocol should be fully distributed; Easy computation and maintenance, Adaptive to frequent topology change, Optimal and loop free route optimal use of resources, Collision should be minimum. MANET detect the shortest path with minimum hop count as optimal route without any consideration traffic and the performance degrading of the network Therefore it is very essential to consider load balancing issue in routing mechanism. We mainly focuses on survey of various load balanced Routing protocols for efficient data transmission in MANETs.","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134305007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparing PSNR by using Integer and Haar Wavelet Transform in Reversible Data Hiding Technique  比较可逆数据隐藏技术中整数小波变换与Haar小波变换的PSNR
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/02.01.06
S. Jeba, Pon Elizabeth
{"title":"Comparing PSNR by using Integer and Haar Wavelet Transform in Reversible Data Hiding Technique ","authors":"S. Jeba, Pon Elizabeth","doi":"10.31838/ijccts/02.01.06","DOIUrl":"https://doi.org/10.31838/ijccts/02.01.06","url":null,"abstract":"2 .Abstract - A novel approach to recover data and cover image was introduced here by using reserve room concept of encryption. Here, data can be extracted without any loss, since reserve room concept of encryption is being used. In the previous methods, data are encrypted and are then being stored. But, in this method, data are stored in a particular place before the process of encryption. This helps in preventing the loss of data occurring in the system. Usually, transformation is a compression technique, takes place in the image to improve its quality. Integer wavelet transform and Haar transform are used here to improve the quality of the image. Comparison of integer wavelet transform and Haar transformation takes place and the PSNR achieved by Haar transform is greater than the PSNR achieved by integer wavelet transform. The mean square error also gets decreases in Haar transformation when compares with the integer wavelet transformation. Experimental results show that this method can embed large amount of data comparing to the","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131276882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DESIGN OF LCU FOR REVERSE AIR BAG HOUSE IN CEMENT INDUSTRY 水泥工业反气囊房lcu的设计
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/07.sp01.07
D. Yuvaraj, Rojinraju, N.Aravindaswin, Rsteni Reyas
{"title":"DESIGN OF LCU FOR REVERSE AIR BAG HOUSE IN CEMENT INDUSTRY","authors":"D. Yuvaraj, Rojinraju, N.Aravindaswin, Rsteni Reyas","doi":"10.31838/ijccts/07.sp01.07","DOIUrl":"https://doi.org/10.31838/ijccts/07.sp01.07","url":null,"abstract":"The term LCU refers to the Local Control Unit. Cement industry may contribute significantly to the air pollution \u0000level in the vicinity of the industry. Large quantities of pulverized material are handled and the main air pollution is \u0000emission of dust. Dust is generated at all stages in cement manufacturing process from quarrying through crushing, \u0000homogenizing, burning, handling and storing to the final distribution. Reverse Air Bag House (RABH) is used to \u0000control industrial particulate pollutants. The term bag house refers to a filtration technology that uses cloth or \u0000synthetic filters for the dust collection. It consists of several bags inside it above the hopper. Dust particles from the \u0000raw mill, pre-heater are fed to this reverse air bag house section. The bag filter filters the dust outside of the bag. \u0000On cleaning the fine dust particles, it falls into the hopper and stores on the silo. Hence 99% of the fresh air is \u0000exhausted outside. The proposed system will automate the Reverse Air Bag House unit separately using PLC and \u0000SCADA.","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"503 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133069394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
"Automated Trolley System for Airport " “机场自动电车系统”
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/05.01.07
R. Suryakumar
{"title":"\"Automated Trolley System for Airport \"","authors":"R. Suryakumar","doi":"10.31838/ijccts/05.01.07","DOIUrl":"https://doi.org/10.31838/ijccts/05.01.07","url":null,"abstract":"Our Baggage Trolley System ensures that the user can easily access their trolley for transportation of their baggage to their respective terminals of the airport. Everyone would like to lower the high cost wherever it is possible. The amount of costs generated by the baggage loss within the air travel is maximum. As the aircraft can only take off if all the checked-in baggage has its owner on board. If not, the baggage has to be offloaded. In the proposed project the user need not to carry the luggage; the trolley will reach its pre-defined terminal. The trolley will be operated by the RFID card reader to identify the location. Load cell is used for the identification of weight of the luggage. This system will provide full security to the luggage. The costs generated by baggage loss are very high for both the airlines and the airports. The application of RFID technology would reduce these costs extremely. The RF transmitter and receiver are used to identify whether the trolley has reached its correct terminal if not the trolley is enrooted to the correct terminal","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"285 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121140495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SYMMETRIC STACKING BINARY COUNTER 对称叠加二进制计数器
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/07.sp01.03
Manish Kumar, A.S.Devika, Kamya Krishnan, S.Jane Selcia
{"title":"SYMMETRIC STACKING BINARY COUNTER","authors":"Manish Kumar, A.S.Devika, Kamya Krishnan, S.Jane Selcia","doi":"10.31838/ijccts/07.sp01.03","DOIUrl":"https://doi.org/10.31838/ijccts/07.sp01.03","url":null,"abstract":"High efficient and fast addition of multiple operands is an essential process in any computational units. The power and \u0000speed efficiency of multiplier circuits is one of critical importance in the overall performance of microcontrollers and \u0000microprocessors. Multiplier circuits are an essential part of an arithmetic logic unit, or a digital signal processor \u0000system for performing convolution, image processing, filtering, and other purposes. The binary multiplication of fixedpoint \u0000numbers and integers ends up in partial products that is used to provide the ultimate product. Adding \u0000those partial products dominates the power consumption and efficiency of the number. A new binary counter design \u0000uses 3- bit stacking circuit, which groups all the “1” bits together, to combine pairs of 3- bit stacks into 6- bit stacks \u0000through novel symmetric method has been proposed. The bit stacks square measure then reborn to binary counts, \u0000producing 6:3 counter circuits with no xor gates on the critical path. This avoidance of xor gates results in faster \u0000designs with efficient area and power utilization. Additionally, using the counters present in proposed system in \u0000existing counter - based Wallace tree multiplier architectures reduces latency and power consumption for 128 and 64 \u0000- bit multipliers. We apply this Counter design in FIR filter Application","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124597059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
DESIGN OF AUTOMATIC NUMBER PLATE RECOGNITION SYSTEM FOR MOVING VEHICLE 移动车辆车牌自动识别系统的设计
International Journal of communication and computer Technologies Pub Date : 2019-01-01 DOI: 10.31838/ijccts/07.sp01.01
A. Mary, M. Bhuvaneswari, N. Haritha, V. Krishnaveni, B. Punithavathisivathanu
{"title":"DESIGN OF AUTOMATIC NUMBER PLATE RECOGNITION SYSTEM FOR MOVING VEHICLE","authors":"A. Mary, M. Bhuvaneswari, N. Haritha, V. Krishnaveni, B. Punithavathisivathanu","doi":"10.31838/ijccts/07.sp01.01","DOIUrl":"https://doi.org/10.31838/ijccts/07.sp01.01","url":null,"abstract":"Automatic Number Plate Recognition (ANPR) system is a process of capturing the image of the number plate of a \u0000vehicle and the captured images are then processed using image processing. The processed image is then compared \u0000with the vehicle database in this system; we also calculate the speed of the vehicle using the sensor unit. The speed \u0000details are displayed on the webpage. This system gives an automatic alert if the vehicle crosses the speed limit. If any \u0000traffic violation occurs the information will be sent to the internet. The stolen vehicles are also detected using RFID \u0000technology. The use of ANPR will be helpful in the place of accidents, and toll collection, tracking stolen cars, red-light \u0000violation enforcement, and border checkpoints.","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131784089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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