Analysis on FPGA Designs of Parallel High Performance Multipliers

For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. In this paper, optimized high performance parallel GF(2 233 ) multipliers for an FPGA realization were designed and the time and area complexities were analyzed. One of the multipliers uses a new hybrid structure to implement the Karatsuba algorithm. For increasing performance, we make excessive use of pipelining and efficient control techniques and use a modern state-of-the-art FPGA technology. As a result we have, to our knowledge, the first hardware realization of sub quadratic arithmetic and currently the fastest and most efficient implementation of 233 bit finite field multipliers.