{"title":"Demonstration of Principal Component Analysis on TI-86","authors":"C. Stuerke","doi":"10.1109/TPSD.2008.4562756","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562756","url":null,"abstract":"We often measure a variety of features when attempting to perform classification. Principal component analysis (PCA) can assist the multivariate investigation by reducing dimensionality and by maximizing feature space variance. For demonstration, this paper shows the techniques for finding the improved feature space and it shows how to project data into this space, using the native commands of the TI-86 calculator.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124276921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Bluetooth Clock Recovery and Hop Sequence Synchronization Using Software Defined Radios","authors":"A. A. Tabassam, S. Heiss","doi":"10.1109/TPSD.2008.4562737","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562737","url":null,"abstract":"Bluetooth communication is based on frequency hopping spread-spectrum and time division duplexing. Bluetooth devices must be properly synchronized so that they can hop together; the synchronization is done by using the same channel set as well as the same hopping sequence within that channel set along with the time synchronization. Frequency hopping sequences are derived from Bluetooth device addresses and clock values. During the inquiry procedure as well as in the page procedure, frequency hop synchronization (FHS) packets are exchanged which contain the device addresses and clock values for the derivation of the frequency hop sequences. This paper presents the different possibilities to intercept and demodulate the frequency hop synchronization packets exchanged during the inquiry or the page procedure. It also presents a complete SDR prototype solution to get the master's device address and its clock value, just listing for a short time on a fixed RF frequency out of the 79 Bluetooth channels, without capturing the FHS packet. The prototype system is build and interfaced with an Ettus's USRP mother board and RFX2400 daughter board using the GNU radio framework.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122744267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enclosed Layout Transistor with Active Region Cutout","authors":"S. Binzaid, J. Attia, R.D. Schrimf","doi":"10.1109/TPSD.2008.4562742","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562742","url":null,"abstract":"An enclosed-layout-transistor (ELT) is modified using the active region cutout (ARC) technique. This transistor is called ARCELT. 3-D simulations were performed to obtain the leakage current with respect to radiation induced charge density, while keeping the layout dimensions and process parameters unchanged, for a standard nMOS transistor, the ELT and the ARCELT. The aspect ratio W/L of ARCELT was found to be smaller than ELT. It is shown that the ARCELT has radiation tolerance similar to that of ELT. The ARCELT can be configured as a triple electrode MOSFET device that can be used to design compound transistors. Two applications of ARCELT as a compound transistor are shown.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129353940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Bhola, H. T. Russell, R. Carter, W. Davis, A. Haque
{"title":"Design and Analysis of an Improved Translinear Floating Resistor for a Variable Gain Amplifier","authors":"S. Bhola, H. T. Russell, R. Carter, W. Davis, A. Haque","doi":"10.1109/TPSD.2008.4562758","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562758","url":null,"abstract":"An enhanced current controlled floating resistor design using a buffered mixed translinear loop based on the exponential current voltage relationship of the bipolar junction transistor is presented. The floating resistance varies from 1 k Ohm to 13 Ohms. Current controlled floating resistors have many applications in the design of electronically tunable analog circuits such as amplifiers, oscillators and active RC filters. This paper discusses the application of this floating resistor as a tuning stage of a variable gain amplifier. The variable gain amplifier has a voltage gain range from 1 to 7. The design was fabricated with National Semiconductor Corporation's vertically integrated complimentary bipolar technology (VIP10) and the test results are presented in this paper.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124351563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Classification of Imagined Motor Tasks for BCI","authors":"P. Doynov, J. Sherwood, R. Derakhshani","doi":"10.1109/TPSD.2008.4562761","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562761","url":null,"abstract":"Electroencephalography (EEG) is a well developed technique used in many clinical and research applications. Continuous improvements on quality of scalp electrodes and front-end amplifiers, and data processing and storage have elevated EEG to a standard non-invasive method for monitoring many brain functions. EEG can also provide a new means for sending messages to the external world which is commonly known as a Brain-Computer Interface (BCI). This paper describes different feature extraction techniques for classification of recorded EEG signals. Time and frequency processing of multichannel EEG recordings during four a priori known mental tasks is presented. The four tasks include imagining the movement of an arm or a leg without the execution of the actual motion. During the recording sessions, the imagined movements are separated with intervals of subject relaxation. Different methods were used for feature extraction and classification of the EEG signals as a base for BCI. The results demonstrate that signals from an untrained subject can be classified successfully. The algorithms can be used to establish a real-time direct connection between mental task activity and external communication. In this regard we view the possibility for extending the neuroplasticity of the brain toward direct control of specifically designed external devices.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"32 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130794473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast Template Matching System Using VHDL","authors":"R. Tate, J. Northern","doi":"10.1109/TPSD.2008.4562754","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562754","url":null,"abstract":"The image template matching problem is one of the fundamental problems of and has many practical applications in image processing, pattern recognition, and computer vision. It is a useful operation for filtering, edge detection, image registration, and object detection. Template matching is the process of determining the presence and the location of a reference image of an object inside a scene image under analysis by a spatial cross-correlation process. Conventional cross- correlation type algorithms are computationally expensive. In this paper, a method of fast image template matching algorithm based on template modeling is proposed. Taken advantage of fast searching techniques, the method can achieve high computing efficiency and good matching results. Furthermore a comparison of the performance provided by this method and conventional matching algorithms is discussed. Theoretical analysis and simulation results show that the proposed algorithm is very effective. Simple hardware architecture is presented and implemented, where it executes matching for a 4times4 template on a 16 times 16 target image.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127804672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mahsa Dornajafi, Steve E. Watkins, Benjamin Cooper, M. Ryan Bales
{"title":"Performance of a Quaternary Logic Design","authors":"Mahsa Dornajafi, Steve E. Watkins, Benjamin Cooper, M. Ryan Bales","doi":"10.1109/TPSD.2008.4562722","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562722","url":null,"abstract":"This paper analyzes the performance of a quaternary logic circuit and its components. The multi-valued logic design consisting of two drivers and a transistor matrix is simulated using Mentor Graphic software. Functional operation of the circuit is shown and propagation delay and power consumption are determined. The design is dependent on the voltage values for the multi-valued logic. Three logic cases are investigated. The performance of the logic circuit as a quaternary difference calculator is described.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127034676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Comparative Study of Linear and Nonlinear Data-Driven Surrogate Models of Human Joints","authors":"J. Sherwood, R. Derakhshani, T. Guess","doi":"10.1109/TPSD.2008.4562759","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562759","url":null,"abstract":"Various linear feed-forward and recurrent data- driven models, as well as their nonlinear counterparts, are studied for dynamic musculoskeletal system identification. It is shown that dynamic neural networks are well suited for black- box modeling of biomechanical multi-body systems, as these nonlinear paradigms could capture human joint force- displacement dynamics with much lower computational complexity compared to traditional methods such as the finite element methods. This paper analyzes the performance of different surrogate model architectures using simulated knee data, and provides comparisons between their drawbacks and benefits such as computational efficiency. While linear models presented acceptable results, the non-linear implementations yielded substantial performance improvements with equal or shorter tapped delay lines over their linear counterparts.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114195010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testing of Asynchronous NULL Conventional Logic (NCL) Circuits","authors":"S. Kakarla, W. Al-Assadi","doi":"10.1109/TPSD.2008.4562764","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562764","url":null,"abstract":"Due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, conventional automatic test pattern generation (ATPG) algorithms would fail when applied to asynchronous circuits, leading to poor fault coverage. This paper focuses on design for test (DFT) techniques aimed at making asynchronous NCL designs testable using existing DFT CAD tools with reasonable gate overhead, by enhancing controllability of feedback nets and observability for fault sites that are flagged unobservable. The proposed approach performs scan and test points insertion on NCL designs using custom ATPG library. The approach has been automated, which is essential for large systems; and are fully compatible with industry standard tools.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116642502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Brief Introduction of Feature Matching","authors":"Dianchao Liu, Samuel Cheng","doi":"10.1109/TPSD.2008.4562728","DOIUrl":"https://doi.org/10.1109/TPSD.2008.4562728","url":null,"abstract":"This paper presents several useful techniques about feature matching. As we know, for virtual worlds 3D reconstruction, we need many good 2D images with more precious correspondent matching points, thus, more realistic 3D models could be reconstructed for computer vision use, medical use or many other vision applications. This paper describes basis of feature matching, and also several further technical methods to achieve better correspondence matching. Experiment results show basic matching methods and different enhanced methods respectively, from which we can get ideas about how to make feature matching better.","PeriodicalId":410786,"journal":{"name":"2008 IEEE Region 5 Conference","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116241025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}