ACM-SE 28最新文献

{"title":"The design of a private key cryptosystem","authors":"M. Januska","doi":"10.1145/98949.99160","DOIUrl":"https://doi.org/10.1145/98949.99160","url":null,"abstract":"In order to design a private key cryptosystem using a layered approach, we must first examine (he basic characteristics of a conventional cryptosystem. A very simple cryplosyslcm has plaintext, a key, ciphertext, a deciphering transformation and an enciphering transformation. Plaintext is defined to be the original text in readable form; for example, (he material you arc now reading. The key is defined as a set of symbols that is used repeatedly when performing the transformations in a deterministic way. An enciphering transformation takes the key and the plaintext, performs a specific function, and outputs the ciphertext. Ciphertext is defined to be the result of this transformation. It cannot be read in the same way as this text because it won’t make any sense. In order to do this the ciphertext must be transformed using a deciphering transformation. When this is done properly, the plaintext is recovered in its original form. Let us now construct a simple cryptosystem using these definitions. The following algorithm will be used: define key = K of 64 bits in length define plaintext = message = M of L in length define ciphertext = C define input buffer = I define output buffer = O while ( <= L) /* message not completely processed */ (get next 64 bits of M and put them in a buffer I XOR (he bits in I with the key K to get C put C in 0 put 0 back in the same position (overwrite) in M | With this simple algorithm, we can do both the encryption and the decryption. This is due to the properties of the XOR operator. The property we are taking advantage of is this: a XOR b -> x, x XOR b -> a. But how do we know that the message is ncrypted? Well, just try to read it, it’s that simple! If gibberish comes up on the screen, you know that the file is encrypted. Just run the algorithm","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131319702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The development of a modula-2 validation suite","authors":"K. N. King, Dave Crick","doi":"10.1145/98949.98999","DOIUrl":"https://doi.org/10.1145/98949.98999","url":null,"abstract":"The Modula-2 Validation Suite (M2VS) is a collection of test programs and related tools that support formal testing of Modula-2 implementations. This paper describes the history of the M2VS, the organization of the M2VS, and plans for future development of the M2VS. A notab'c feature of the suite is the execution monitor, which sup­ ports automated testing and cross-compiler testing.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130585771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Elements of a senior design projects course","authors":"Stephen M. Jodis, P. Maine","doi":"10.1145/98949.98997","DOIUrl":"https://doi.org/10.1145/98949.98997","url":null,"abstract":"The Senior Design Projects course at Auburn University (two consecutive terms) gives undergraduate students a significant research experience by developing a project from proposal to prototype phase. Project ideas arc obtained from faculty, graduate students, and persons outside the university. Student groups of three or four members are formed through use of a written survey; and a group is assigned to a project. The groups then proceed through the phases of the software life cycle including project proposal, system requirements, architectural design, system design, and prototype development. The knowledge acquired in working on a nontrivial project has proven beneficial to the students in future employment and graduate studies.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114009239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A neural network for sonar target recognition","authors":"Michael O'Rourke, J. Wood","doi":"10.1145/98949.99150","DOIUrl":"https://doi.org/10.1145/98949.99150","url":null,"abstract":"This paper explores the area of sonar target recognition us­ ing a feedforward neural network trained with the backpropagation algorithm. Sixteen sonar waves from a variety of targets were used in the experiment Noise was introduced to each waveform at 13,10, and 3 db signal to noise ratio. The network was trained with different com­ binations of the noisy waveforms and tested with noisy data not used in the training process. 100% correct classi­ fication was obtained in all cases.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126539605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Finding parents in a heap","authors":"Fred L. Heller","doi":"10.1145/98949.99113","DOIUrl":"https://doi.org/10.1145/98949.99113","url":null,"abstract":"In tliis paper we explore the problem of adding a new node to a heap ADT implemented using linked storage. Specifically, we present an 0(log(n)) algorithm to find the next parent node in order to maintain the complete binary tree property of a heap. When the nodes in a heap are numbered breadth first, there exists a relationship between the node numbers and the level of the tree which uniquely determines a path from the current parent node to the next parent node in a heap.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130962493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Approaches to solving synchronization problems in parallel simulation of an apparel plant","authors":"P. Khambekar, S. Dharmaraj","doi":"10.1145/98949.99143","DOIUrl":"https://doi.org/10.1145/98949.99143","url":null,"abstract":"A near-term computer simulation of an apparel in­ dustry shop-floor is an application of interest. The complexity and the natural parallelism of the applica­ tion suggest a parallel implementation. Parallelizing a simulation causes synchronization problems. These problems are analyzed, various solutions presented and short-comings or inapplicability to the application de­ scribed. A method which is an adaptation of a previ­ ously published method is then presented. This con­ servative method produces an accurate simulation. I n tr o d u c t io n Clemson University is currently developing a nearterm computer simulation of an apparel factory floor. Given inputs of employee assignments, arrival of new bundles of garment parts, priorities of bundles, etc. (i.e. a tentative plan), the flow of bundles being sewn during the course of a day is simulated and high-level performance information in the form of graphics is dis­ played to the plant manager (the user). The manager should be able to run the simulation, evaluate the per­ formance metrics and in case they are not satisfactory, roll-back the simulation to a specified point in time and rerun the simulation with a new plan all in a matter of minutes. This simulation will provide a valuable tool for achieving Just-In-Time manufacturing. In a typical plant, there are hundreds of ma­ chines, hundreds of employees and thousands of bun­ dles containing garment parts. The complexity of the application, large input data, large number of metrics, quick simulation requirement and natural parallelism of the application strongly suggest performing the sim­ ulation in parallel. Unfortunately, in a general-purpose parallel simulation two synchronization problems may occur: deadlock and no-progress. This paper describes the methods planned to address these problems. Peniiinnlon lo copy wllliout fee all or part of this material la granted provided that the copiea are not made or distributed for direct com­ mercial advantage, the ACM copyright notice and the title of llie publication and Its dale appear, and notice ia given that copying ja by pcmtlsaion of llie Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific per­ mission. Section 2 describes the apparel manufacturing environment. The parallelization of the application is described in Section 3. Section 4 describes the syn­ chronization problems posed by the parallel simula­ tion. A survey of the methods given in the literature to solve the problems is provided in Section 5. The method chosen for this implementation is described in Section 6. T h e A p p a r e l F a c to r y S h o p -F lo o r On the factory floor bundles of garment parts are pro­ cessed according to a style flow graph, an example of which is given in Figure 1. Rectangles in the figure represent buffers which have work waiting for oper­ ations to be performed. Examples of operations are \"set pocket” and \"attach buttons”. There is a one-toone corr","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122800358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the feasibility of automatically generating data flow diagrams from ada","authors":"Kelly I. Morrison","doi":"10.1145/98949.99148","DOIUrl":"https://doi.org/10.1145/98949.99148","url":null,"abstract":"Introduction The recovery of high-level system documentation from source code involves two major steps, the formalization of a set of appropriate high-level graphical constructs with which to describe the target documentation, and the map­ ping of source code to these constructs. Auburn Universi­ ty’s GRASP/Ada (Graphical Representation of Algo­ rithms, Structure, and Processes for Ada) project [1] pro­ poses to define a documentation model based on the Data Flow Diagram (DFD) and design a recovery tool to pro­ duce designs conforming to this model. At present, the GRASP/Ada project is examining the GRASP/GT (Graphical Approach to the Specification of Programs/ Graphics and Text) model proposed by Morrison [2] to de­ termine its suitability for this purpose. This paper presents the current findings of this phase of the project.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116354658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of grain size on the performance of systolic array","authors":"Ravi Varadaragan, Bhavai Ravichandran","doi":"10.1145/98949.99041","DOIUrl":"https://doi.org/10.1145/98949.99041","url":null,"abstract":"Systolic arrays belong to a class of pipelined ar­ ray architectures useful for hardware implementation of compute-bound algorithms. The design of sys­ tolic arrays involves mapping the computations on to the processors that operate in a synchronized fash­ ion in such a way that the data needed in a com­ putation arrive at the right processor at the right time. Automatic or semi-automatic mapping tools are necessary for the synthesis of systolic arrays with different trade-olfs between execution time and processor-memory requirements. Lamport [1] used a hyperplane technique for allocating nested itera­ tions onto asynchronous parallel processors. A gen­ eral technique for mapping nested loop algorithms on to multi-dimensional systolic arrays was proposed by Moldovan and Fortes [3]. A similar technique was proposed by Lee and Kedem [2] for mapping nested loops on to linear arrays based on Lamport’s [1] hypcrplane method. When each iteration in the nested loop has a num­ ber of statements or operations, then all these tech­ niques do not address the issue of how to partition each iteration into proper grain sizes to allow partial overlapping of dependent iterations. In our work, we have demonstrated how different grain sizes chosen for partitioning the iterations can affect the perfor­ mance of systolic arrays as measured by execution time, buffer storage, processor utilization etc.. Our results indicate the need for addressing the issue of choosing proper grain sizes in mapping algorithms onto systolic arrays. We focus our attention on mapping nested loop algorithms that can be synchronized either at the statement level or at the iteration level. Existing techniques for mapping do not allow asynchronous execution of iterations. The dependencies that ex-","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129828606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Three approaches to design fault tolerant programmable logic arrays","authors":"S. Al-Arian, H.P. Kunamneni","doi":"10.1145/98949.99035","DOIUrl":"https://doi.org/10.1145/98949.99035","url":null,"abstract":"The objective of this paper is to design Fault Tolerant Program m able Logic Arrays (FTPLA). The task of designing FTPLA's can be divided in two parts: fault detection and fault correction or masking. Three ap p roach es to a ch iev e this objective are presented. The fault detection step is ach ieved through designing a self-checking circuit for each approach. On the other hand, the fault correction capability is achieved through three different and distinct techniques. The first approach im plem ents hardware redundancy, w here m-out-of-n c o d e s are considered with replication. The second approach however, u ses time redundancy, where alternating logic is Implemented and the checker is designed using kout of-2k co d es. In the third technique, another input Is added and the data retry technique is employed. The outputs of the PLA are connected to D-latches and the network outputs are taken from a common bus. All Three techniques are applied and the PLA's are realized. In addition the overhead for each approach is evaluated.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133152399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integration of a workstation laboratory into a computer science curriculum","authors":"W. A. Ward","doi":"10.1145/98949.98995","DOIUrl":"https://doi.org/10.1145/98949.98995","url":null,"abstract":"This paper describes the integration of a worksta­ tion laboratory, jointly funded by the National Science Foundation and by the University of South Alabama, into a computer science curriculum. The laboratory contains a Sun hie server and five diskless workstations and is part of a departmental local area network. The project's overall goal was to provide a window-oriented, graphics environment for undergraduate computer science stu­ dents; use of the laboratory in several courses is dis­ cussed to show how this goal has been reached. Details of the project are presented, including background infor­ mation, project objectives, equipment selection, labora­ tory utilization, and problems and their resolution. The paper concludes with remarks on lessons learned in the course of this project, unanticipated benefits, and future plans.","PeriodicalId":409883,"journal":{"name":"ACM-SE 28","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114187701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}