Three approaches to design fault tolerant programmable logic arrays

Abstract

The objective of this paper is to design Fault Tolerant Program m able Logic Arrays (FTPLA). The task of designing FTPLA's can be divided in two parts: fault detection and fault correction or masking. Three ap p roach es to a ch iev e this objective are presented. The fault detection step is ach ieved through designing a self-checking circuit for each approach. On the other hand, the fault correction capability is achieved through three different and distinct techniques. The first approach im plem ents hardware redundancy, w here m-out-of-n c o d e s are considered with replication. The second approach however, u ses time redundancy, where alternating logic is Implemented and the checker is designed using kout of-2k co d es. In the third technique, another input Is added and the data retry technique is employed. The outputs of the PLA are connected to D-latches and the network outputs are taken from a common bus. All Three techniques are applied and the PLA's are realized. In addition the overhead for each approach is evaluated.