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Proceedings of International Conference on Computer Aided Design最新文献

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An algorithm for power estimation in switched-capacitor circuits 一种开关电容电路的功率估计算法
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569837
Chad Young, G. Casinovi, J. Fowler, P. Kerstetter
{"title":"An algorithm for power estimation in switched-capacitor circuits","authors":"Chad Young, G. Casinovi, J. Fowler, P. Kerstetter","doi":"10.1109/ICCAD.1996.569837","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569837","url":null,"abstract":"A number of low-power designs, such as those for mobile communication equipment, contain switched-capacitor circuits. In such designs it is important to be able to estimate the power dissipated by the switched-capacitor portion of the circuit. This paper describes an algorithm for the computation of statistical information about the power dissipated in a switched-capacitor circuit when corresponding statistical information about the inputs to the circuit is known. Ordinary circuit simulators are not suited for this task. Because they can only compute the power dissipated by the circuit for one specific set of input signals. The algorithm does not require Monte-Carlo analyses, and it accounts for correlation among the inputs. To demonstrate the algorithm's performance, numerical results obtained on a number of sample switched-capacitor circuits are reported.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128154635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploiting regularity for low-power design 利用规律进行低功耗设计
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569540
Renu Mehra, J. Rabaey
{"title":"Exploiting regularity for low-power design","authors":"Renu Mehra, J. Rabaey","doi":"10.1109/ICCAD.1996.569540","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569540","url":null,"abstract":"Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized designs, about 10 to 40% of the total power may be dissipated in buses, multiplexors, and drivers. We present a novel approach targeted at the reduction of power dissipation in interconnect elements-buses, multiplexors, and buffers. The scheduling, assignment, and allocation techniques presented in this paper exploit the regularity and common computational patterns in the algorithm to reduce the fan-outs and fan-ins of the interconnect wires, resulting in reduced bus capacitances and a simplified interconnect structure. Average power savings of 47% and 49% in buses and multiplexors, respectively, are demonstrated on a set of benchmark examples.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124224748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 68
Simulation-based techniques for dynamic test sequence compaction 基于仿真的动态测试序列压缩技术
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.568942
E. Rudnick, J. Patel
{"title":"Simulation-based techniques for dynamic test sequence compaction","authors":"E. Rudnick, J. Patel","doi":"10.1109/ICCAD.1996.568942","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.568942","url":null,"abstract":"Simulation-based techniques for dynamic compaction of test sequences are proposed. The first technique uses a fault simulator to remove test vectors from the partially-specified test sequence generated by a deterministic test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in the partially-specified test sequence in order to increase the number of faults detected by the sequence. Significant reductions in test set sizes were observed for all benchmark circuits studied. Fault coverages improved for many of the circuits, and execution times often dropped as well, since fewer faults had to be targeted by the computation-intensive deterministic test generator.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121842288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data 具有测量或表格数据的线性子网络矩匹配仿真的有效方法
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.568904
G. Zheng, Qi-jun Zhang, M. Nakhla, R. Achar
{"title":"An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data","authors":"G. Zheng, Qi-jun Zhang, M. Nakhla, R. Achar","doi":"10.1109/ICCAD.1996.568904","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.568904","url":null,"abstract":"This paper describes a new moment-generation algorithm for efficient simulation of linear subnetworks characterized by measured or tabulated data using moment-matching techniques. The subnetwork moments are computed by performing an integration in time-domain on the measured data. The proposed technique is more accurate as it relies on integration as compared to the previously published approaches which depend on the differentiation of measured data in frequency-domain for computation of moments. Using the new moment-generation technique, the CFH (Complex Frequency Hopping) algorithm has been extended to handle measured subnetworks. Also a generalized stencil for measured data for inclusion in circuit simulators and to facilitate efficient moment-generation has been presented. Examples and comparison with conventional simulations are provided. The method is accurate while it is faster than the conventional approach by 1 to 2 orders of magnitude.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121969519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A video driver system designed using a top-down, constraint-driven methodology 一个视频驱动系统设计使用自顶向下，约束驱动的方法
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569839
I. Vassiliou, Henry Chang, A. Demir, E. Charbon, Paolo Miliozzi, A. Sangiovanni-Vincentelli
{"title":"A video driver system designed using a top-down, constraint-driven methodology","authors":"I. Vassiliou, Henry Chang, A. Demir, E. Charbon, Paolo Miliozzi, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1996.569839","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569839","url":null,"abstract":"To accelerate the design cycle for analog and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. The key idea of the proposed methodology is hierarchically propagating constraints from performance specifications to layout. Consequently, it is essential to provide the necessary tools and techniques enabling the efficient constraint propagation. To illustrate the applicability of the proposed methodology to the design of larger systems, we present in this paper the complete design flow for a video driver system. Critical advantages of the methodology illustrated with this design example include avoiding costly low level re-designs and getting working silicon parts from the first run. Following our approach, a jitter constraint is imposed at the system level and then is propagated hierarchically to the circuit blocks and layout, using behavioral modeling and simulation. Experimental results are presented from working fabricated parts.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131785641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A new method towards achieving global optimality in technology mapping 一种实现技术映射全局最优的新方法
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.568902
X. Wen, K. Saluja
{"title":"A new method towards achieving global optimality in technology mapping","authors":"X. Wen, K. Saluja","doi":"10.1109/ICCAD.1996.568902","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.568902","url":null,"abstract":"This paper presents a new method for covering a Boolean network by library cells. In this method, matches are classified according to their properties. Some matches are selected unconditionally into a cover and the remaining nodes are divided into independent portions. Then, a match compatibility graph (MCG) is constructed for each portion and an optimum cover is found for it using the MCG. Thus our method finds an efficient and closer to optimum cover for the complete network.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129442630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Clock skew optimization for ground bounce control 时钟倾斜优化地面弹跳控制
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569827
A. Vittal, Hein Ha, F. Brewer, M. Marek-Sadowska
{"title":"Clock skew optimization for ground bounce control","authors":"A. Vittal, Hein Ha, F. Brewer, M. Marek-Sadowska","doi":"10.1109/ICCAD.1996.569827","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569827","url":null,"abstract":"High speed synchronous digital systems require large switching currents to facilitate rapid signal transitions. These large currents create voltage drops on the power distribution network and necessitate expensive chip packaging with a large number of supply pins. In this paper we propose a novel technique to reduce the dynamic transient current drawn from the supply pins. Our approach is based on sub-dividing the synchronous clocking into multiple sub-clocks with relative skew. This spreads the computation across the entire clock cycle instead of largely occurring at the beginning. Timing constraints must also be obeyed, so that no races or timing errors are introduced. We propose an exact algorithm based on integer linear programming to solve this problem. We have used our method in the design of a 5 GHz ECL encoder chip to achieve a factor of two reduction in ground bounce, as shown by HSPICE simulations. We also obtained order-of-magnitude improvements in ground bounce on benchmarks laid our in submicron CMOS technology. The approach potentially leads to significant reductions in packaging costs.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114243967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
Directional bias and non-uniformity in FPGA global routing architectures FPGA全局路由架构中的方向偏置和非均匀性
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.571342
Vaughn Betz, Jonathan Rose
{"title":"Directional bias and non-uniformity in FPGA global routing architectures","authors":"Vaughn Betz, Jonathan Rose","doi":"10.1109/ICCAD.1996.571342","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.571342","url":null,"abstract":"We investigate the effect of the prefabricated routing track distribution on the area-efficiency of FPGAs. The first question we address is whether horizontal and vertical channels should contain the same number of tracks (capacity), or if there is a density advantage with a directional bias. Secondly, should the channels have a uniform capacity, or is there an advantage when capacities vary from channel to channel? The key result is that the most area-efficient global routing architecture is one with uniform (or very nearly uniform) channel capacities across the entire chip in both the horizontal and vertical directions. Several non-uniform and directionally-biased architectures, however are fairly area-efficient provided that appropriate choices are made for the pin positions on the logic blocks and the logic array aspect ratio.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131854474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 82
CTL model checking based on forward state traversal 基于前向状态遍历的CTL模型检测
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569084
H. Iwashita, T. Nakata, F. Hirose
{"title":"CTL model checking based on forward state traversal","authors":"H. Iwashita, T. Nakata, F. Hirose","doi":"10.1109/ICCAD.1996.569084","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569084","url":null,"abstract":"We present a CTL model checking algorithm based mainly on forward state traversal, which can check many realistic CTL properties without doing backward state traversal. This algorithm is effective in many situations where backward state traversal is more expensive than forward state traversal. We combine it with BDD-based state traversal techniques using partitioned transition relations. Experimental results show that our method can verify actual CTL properties of large industrial models which cannot be handled by conventional model checkers.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124237119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
An optimal algorithm for river routing with crosstalk constraints 具有串扰约束的河流路由优化算法
Proceedings of International Conference on Computer Aided Design Pub Date : 1996-11-10 DOI: 10.1109/ICCAD.1996.569717
H. Zhou, Martin D. F. Wong
{"title":"An optimal algorithm for river routing with crosstalk constraints","authors":"H. Zhou, Martin D. F. Wong","doi":"10.1109/ICCAD.1996.569717","DOIUrl":"https://doi.org/10.1109/ICCAD.1996.569717","url":null,"abstract":"With the increasing density of VLSI circuits, the interconnection wires are getting packed even closer. This has increased the effect of interaction between these wires on circuit performance and hence, the importance of controlling crosstalk. We consider river routing with crosstalk constraints. Given the positions of the pins in a single-layer routing channel and the maximum tolerable crosstalk between each pair of nets, we give a polynomial time algorithm to decide whether there is a feasible river routing solution and produce one with minimum crosstalk whenever the problem is feasible.","PeriodicalId":408850,"journal":{"name":"Proceedings of International Conference on Computer Aided Design","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115582642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
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