Clock skew optimization for ground bounce control

High speed synchronous digital systems require large switching currents to facilitate rapid signal transitions. These large currents create voltage drops on the power distribution network and necessitate expensive chip packaging with a large number of supply pins. In this paper we propose a novel technique to reduce the dynamic transient current drawn from the supply pins. Our approach is based on sub-dividing the synchronous clocking into multiple sub-clocks with relative skew. This spreads the computation across the entire clock cycle instead of largely occurring at the beginning. Timing constraints must also be obeyed, so that no races or timing errors are introduced. We propose an exact algorithm based on integer linear programming to solve this problem. We have used our method in the design of a 5 GHz ECL encoder chip to achieve a factor of two reduction in ground bounce, as shown by HSPICE simulations. We also obtained order-of-magnitude improvements in ground bounce on benchmarks laid our in submicron CMOS technology. The approach potentially leads to significant reductions in packaging costs.