37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)最新文献_第7页

Scaling and Continuous Availability in Database Server Clusters through Multiversion Replication 通过多版本复制在数据库服务器集群中扩展和持续可用性

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.86

Kaloian Manassiev, C. Amza

{"title":"Scaling and Continuous Availability in Database Server Clusters through Multiversion Replication","authors":"Kaloian Manassiev, C. Amza","doi":"10.1109/DSN.2007.86","DOIUrl":"https://doi.org/10.1109/DSN.2007.86","url":null,"abstract":"In this paper, we study replication techniques for scaling and continuous operation for a dynamic content server. Our focus is on supporting transparent and fast reconfiguration of its database tier in case of overload or failures. We show that the data persistence aspects can be decoupled from reconfiguation of the database CPU. A lightweight in-memory middleware tier captures the typically heavyweight read-only requests to ensure flexible database CPU scaling and fail-over. At the same time, updates are handled by an on-disk database back-end that is in charge of making them persistent. Our measurements show instantaneous, seamless reconfiguration in the case of single node failures within the flexible in-memory tier for a web site running the most common, shopping, workload mix of the industry-standard e- commerce TPC-W benchmark. At the same time, a 9-node in-memory tier improves performance during normal operation over a stand-alone InnoDB on-disk database back- end. Throughput scales by factors of 14.6, 17.6 and 6.5 for the browsing, shopping and ordering mixes of the TPC-W benchmark, respectively.","PeriodicalId":405751,"journal":{"name":"37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131688985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays 纳米电子可编程逻辑阵列的容错方法

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.49

Wenjing Rao, A. Orailoglu, R. Karri

引用次数: 22

Knowledge Connectivity vs. Synchrony Requirements for Fault-Tolerant Agreement in Unknown Networks 未知网络中容错协议的知识连通性与同步需求

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.61

F. Greve, S. Tixeuil

引用次数: 66

Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning 通过可靠的动态时钟频率调谐来增强超标量处理器性能

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.90

Viswanathan Subramanian, M. Bezdek, N. D. Avirneni, Arun Kumar Somani

{"title":"Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning","authors":"Viswanathan Subramanian, M. Bezdek, N. D. Avirneni, Arun Kumar Somani","doi":"10.1109/DSN.2007.90","DOIUrl":"https://doi.org/10.1109/DSN.2007.90","url":null,"abstract":"Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, this has special implications since the operating frequency of the entire pipeline is limited by the slowest stage. Our goal, in this paper, is to achieve higher performance in superscalar processors by dynamically varying the operating frequency during run time past worst case limits. The key objective is to see the effect of overclocking on superscalar processors for various benchmark applications, and analyze the associated overhead, in terms of extra hardware and error recovery penalty, when the clock frequency is adjusted dynamically. We tolerate timing errors occurring at speeds higher than what the circuit is designed to operate at by implementing an efficient error detection and recovery mechanism. We also study the limitations imposed by minimum path constraints on our technique. Experimental results show that an average performance gain up to 57% across all benchmark applications is achievable.","PeriodicalId":405751,"journal":{"name":"37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127099585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

On the Cost of Modularity in Atomic Broadcast 原子广播中模块化的代价

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.69

Olivier Rütti, Sergio Mena, Richard Ekwall, A. Schiper

引用次数: 2

A Framework for Architecture-Level Lifetime Reliability Modeling 体系结构级寿命可靠性建模框架

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.8

Jeonghee Shin, V. Zyuban, Zhigang Hu, J. Rivers, P. Bose

引用次数: 66

Insights into the Sensitivity of the BRAIN (Braided Ring Availability Integrity Network)--On Platform Robustness in Extended Operation 对BRAIN(编织环可用性完整性网络)敏感性的洞察——关于扩展操作中的平台鲁棒性

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.60

M. Paulitsch, B. Hall

{"title":"Insights into the Sensitivity of the BRAIN (Braided Ring Availability Integrity Network)--On Platform Robustness in Extended Operation","authors":"M. Paulitsch, B. Hall","doi":"10.1109/DSN.2007.60","DOIUrl":"https://doi.org/10.1109/DSN.2007.60","url":null,"abstract":"Low-cost fault-tolerant systems design presents a continual trade-off between improving fault-tolerant properties and accommodating cost constraints. With limited hardware options and to justify the system design rationale, it is necessary to formulate a fault hypothesis to bound failure assumptions. The system must be built on a foundation of real-world relevance and the assumption of coverage of the fault hypothesis. This paper discusses a study that examines the sensitivity of a BRAIN (braided ring availability integrity network) design to different fault types and failure rates in a safety-relevant application. It presents a Markov-based model (using ASSIST, SURE, and STEM analysis tools) and a series of experiments that were run to analyze the overall dependability of the BRAIN approach. The study evaluates the mission reliability and safety in the context of a hypothetical automotive integrated x-by-wire architecture on top of the BRAIN. Drawing from experience in the aerospace domain, the authors investigate the possibility of continued operation for a limited period after a detected critical electronic failure. Continued operation would allow a driver to reach repair facilities rather than stopping the vehicle to call for roadside assistance or \"limping home.\"","PeriodicalId":405751,"journal":{"name":"37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116664351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor 利用动态耦合核形成弹性芯片多处理器

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.100

Christopher LaFrieda, Engin Ipek, José F. Martínez, R. Manohar

{"title":"Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor","authors":"Christopher LaFrieda, Engin Ipek, José F. Martínez, R. Manohar","doi":"10.1109/DSN.2007.100","DOIUrl":"https://doi.org/10.1109/DSN.2007.100","url":null,"abstract":"Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Existing fault-tolerant CMP proposals that implement dual modular redundancy (DMR) do so by statically binding pairs of adjacent cores via dedicated communication channels and buffers. This can result in unnecessary power and performance losses in cases where one core is defective (in which case the entire DMR pair must be disabled), or when cores exhibit different frequency/leakage characteristics due to process variations (in which case the pair runs at the speed of the slowest core). Static DMR also hinders power density/thermal management, as DMR pairs running code with similar power/thermal characteristics are necessarily placed next to each other on the die. We present dynamic core coupling (DCC), an architectural technique that allows arbitrary CMP cores to verify each other's execution while requiring no static core binding at design time or dedicated communication hardware. Our evaluation shows that the performance overhead of DCC over a CMP without fault tolerance is 3% on SPEC2000 benchmarks, and is within 5% for a set of scalable parallel scientific and data mining applications with up to eight threads (16 processors). Our results also show that DCC has the potential to significantly outperform existing static DMR schemes.","PeriodicalId":405751,"journal":{"name":"37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128349311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 145

Quantifying the Effectiveness of Mobile Phone Virus Response Mechanisms 量化手机病毒应对机制的有效性

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.78

E. V. Ruitenbeek, T. Courtney, W. Sanders, F. Stevens

引用次数: 40

Enhanced Reliability Modeling of RAID Storage Systems 改进的RAID存储系统可靠性建模

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) Pub Date : 2007-06-25 DOI: 10.1109/DSN.2007.41

J. Elerath, M. Pecht

引用次数: 105