2013 IEEE 31st International Conference on Computer Design (ICCD)最新文献_第7页

Equivalence checking of partial designs using dependency quantified Boolean formulae 基于依赖量化布尔公式的部分设计等价性检验

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-11-07 DOI: 10.1109/ICCD.2013.6657071

Karina Gitina, Sven Reimer, M. Sauer, Ralf Wimmer, Christoph Scholl, B. Becker

引用次数: 45

Speculative tag access for reduced energy dissipation in set-associative L1 data caches 在集合关联L1数据缓存中减少能量耗散的推测标签访问

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-11-07 DOI: 10.1109/ICCD.2013.6657057

Alen Bardizbanyan, Magnus Själander, D. Whalley, P. Larsson-Edefors

引用次数: 11

Resonant frequency divider design methodology for dynamic frequency scaling 动态频率标度的谐振分频器设计方法

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-11-07 DOI: 10.1109/ICCD.2013.6657087

Y. Teng, B. Taskin

引用次数: 7

Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine 在执行迁移机中为简单性和有效验证进行设计权衡

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-11-07 DOI: 10.1109/ICCD.2013.6657037

Keun Sup Shim, Mieszko Lis, Myong Hyon Cho, Ilia A. Lebedev, S. Devadas

{"title":"Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine","authors":"Keun Sup Shim, Mieszko Lis, Myong Hyon Cho, Ilia A. Lebedev, S. Devadas","doi":"10.1109/ICCD.2013.6657037","DOIUrl":"https://doi.org/10.1109/ICCD.2013.6657037","url":null,"abstract":"As transistor technology continues to scale, the architecture community has experienced exponential growth in design complexity and significantly increasing implementation and verification costs. Moreover, Moore's law has led to a ubiquitous trend of an increasing number of cores on a single chip. Often, these large-core-count chips provide a shared memory abstraction via directories and coherence protocols, which have become notoriously error-prone and difficult to verify because of subtle data races and state space explosion. Although a very simple hardware shared memory implementation can be achieved by simply not allowing ad-hoc data replication and relying on remote accesses for remotely cached data (i.e., requiring no directories or coherence protocols), such remote-access-based directoryless architectures cannot take advantage of any data locality, and therefore suffer in both performance and energy. Our recently taped-out 110-core shared-memory processor, the Execution Migration Machine (EM2), establishes a new design point. On the one hand, EM2 supports shared memory but does not automatically replicate data, and thus preserves the simplicity of directoryless architectures. On the other hand, it significantly improves performance and energy over remote-access-only designs by exploiting data locality at remote cores via fast hardware-level thread migration. In this paper, we describe the design choices made in the EM2 chip as well as our choice of design methodology, and discuss how they combine to achieve design simplicity and verification efficiency. Even though EM2 is a fairly large design-110 cores using a total of 357 million transistors-the entire chip design and implementation process (RTL, verification, physical design, tapeout) took only 18 man-months.","PeriodicalId":398811,"journal":{"name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125355969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Sneak path testing and fault modeling for multilevel memristor-based memories 基于多电平忆阻器的存储器的潜行路径测试和故障建模

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-11-07 DOI: 10.1109/ICCD.2013.6657045

Sachhidh Kannan, R. Karri, O. Sinanoglu

引用次数: 20

On design vulnerability analysis and trust benchmarks development 设计漏洞分析与信任基准开发

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-11-07 DOI: 10.1109/ICCD.2013.6657085

H. Salmani, M. Tehranipoor, R. Karri

{"title":"On design vulnerability analysis and trust benchmarks development","authors":"H. Salmani, M. Tehranipoor, R. Karri","doi":"10.1109/ICCD.2013.6657085","DOIUrl":"https://doi.org/10.1109/ICCD.2013.6657085","url":null,"abstract":"The areas of hardware security and trust have experienced major growth over the past several years. However, research in Trojan detection and prevention lacks standard benchmarks and measurements, resulting in inconsistent research outcomes, and ambiguity in analyzing strengths and weaknesses in the techniques developed by different research teams and their advancements to the state-of-the-art. We have developed innovative methodologies that, for the first time, more effectively address the problem. We have developed a vulnerability analysis flow. The flow determines hard-to-detect areas in a circuit that would most probably be used for Trojan implementation to ensure a Trojan goes undetected during production test and extensive functional test analysis. Furthermore, we introduce the Trojan detectability metric to quantify Trojan activation and effect. This metric offers a fair comparison for analyzing weaknesses and strengths of Trojan detection techniques. Using these methodologies, we have developed a large number of trust benchmarks that are available for use by the public, as well as researchers and practitioners in the field.","PeriodicalId":398811,"journal":{"name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115076531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 209

Long term sustainability of differentially reliable systems in the dark silicon era 暗硅时代差分可靠系统的长期可持续性

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-11-07 DOI: 10.1109/ICCD.2013.6657027

Jason M. Allred, Sanghamitra Roy, Koushik Chakraborty

{"title":"Long term sustainability of differentially reliable systems in the dark silicon era","authors":"Jason M. Allred, Sanghamitra Roy, Koushik Chakraborty","doi":"10.1109/ICCD.2013.6657027","DOIUrl":"https://doi.org/10.1109/ICCD.2013.6657027","url":null,"abstract":"As transistor miniaturization continues, providing robustness and computational correctness comes with rising power, performance, and area overhead costs. However, the diversity of software error tolerance is increasing as modern society embraces ubiquitous computing. This diversity can be exploited by differentially reliable (DR) multicore systems. The rising level of dark silicon-the portion of a chip that must remain inactive due to power budget constraints-makes such DR systems even more attractive when compared to homogeneous designs because power efficiency is improved with the increased flexibility of dynamically selecting appropriate cores for a given software workload. However, ensuring the long-term sustainability of these DR systems is a profound challenge. Asymmetric utilization of cores, differential aging degradation, and manufacturing process variation alter the relative reliability of DR system components, degrading and even eliminating the energy efficiency advantage. In this paper, we propose a feedback control based thread-to-core mapping framework to ensure longterm sustainability and extend the energy efficiency of a DR system. Over a ten-year lifespan, we analyze our approach on two DR design techniques and respectively demonstrate 14.4-16.3% and 26.1-31.0% in sustained energy-efficiency benefits, surpassing the recently proposed race-to-idle approach.","PeriodicalId":398811,"journal":{"name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115060536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Algorithm clustering for multi-algorithm processor design 算法聚类多算法处理器设计

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-10-06 DOI: 10.1109/ICCD.2013.6657080

Madhushika M. E. Karunarathna, Yu-Chu Tian, C. Fidge, R. Hayward

引用次数: 4

Dynamic AC-scheduling for hardware cores with unknown and uncertain information 具有未知和不确定信息的硬件核动态交流调度

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-10-01 DOI: 10.1109/ICCD.2013.6657086

S. Lovergine, Fabrizio Ferrandi

{"title":"Dynamic AC-scheduling for hardware cores with unknown and uncertain information","authors":"S. Lovergine, Fabrizio Ferrandi","doi":"10.1109/ICCD.2013.6657086","DOIUrl":"https://doi.org/10.1109/ICCD.2013.6657086","url":null,"abstract":"Modern hardware cores necessarily have to deal with many sources of unknown or uncertain information. Components with variable latency and unpredictable behavior are becoming predominant in hardware designs. Conventional hardware cores underperform when dealing with unknown or uncertain information. Common High-Level Synthesis (HLS) approaches, which require to specify the complete behavior at design-time, present significant restrictions in supporting this kind of conditions. The literature proposes several dynamic scheduling techniques to improve the cores performance by handling inherent uncertainty of applications. However, they do not address other sources of unknown information. In this paper, we propose the dynamic Activating Conditions (AC)-scheduling: a methodology for the design automation of hardware cores which can dynamically adapt the instructions scheduling according to behaviors unknown at design-time. Neither assumptions about components latency nor worst case approach are required. Experimental results show significant performance increase, with limited area overhead, with respect to state-of-the-art approaches.","PeriodicalId":398811,"journal":{"name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133824432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Data placement in HPC architectures with heterogeneous off-chip memory 具有异质片外存储器的高性能计算架构中的数据放置

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-10-01 DOI: 10.1109/ICCD.2013.6657042

Milan Pavlović, Nikola Puzovic, Alex Ramírez

{"title":"Data placement in HPC architectures with heterogeneous off-chip memory","authors":"Milan Pavlović, Nikola Puzovic, Alex Ramírez","doi":"10.1109/ICCD.2013.6657042","DOIUrl":"https://doi.org/10.1109/ICCD.2013.6657042","url":null,"abstract":"The performance of HPC applications is often bounded by the underlying memory system's performance. The trend of increasing the number of cores on a chip imposes even higher memory bandwidth and capacity requirements. The limitations of traditional memory technologies are pushing research in the direction of hybrid memory systems that, besides DRAM, include one or more modules based on some of the higher-density non-volatile memory technologies, where one of them will provide the required bandwidth, while the other will provide the required capacity for the application. This creates many challenges with data placement and migration policies between the modules of such hybrid memory system. In this paper, we propose an architecture with a hybrid memory design that places two technologically different memory modules in a flat address space. On such system, we evaluate several HPC workloads against different data placement and migration policies, compare their performance by means of execution time and the number of non-volatile memory writes, and consider how it can be applied to the future HPC architectures. Our results show that the hybrid memory system with dynamic page migration and limited DRAM capacity, can achieve performance that is comparable to a hypothetical, hard to implement, DRAM-only system.","PeriodicalId":398811,"journal":{"name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130059655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20