Sneak path testing and fault modeling for multilevel memristor-based memories

Abstract

Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation, compactness and ability to store multiple bits in a single cell. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in multi-level cells (MLC) using memristors and develop efficient fault models. We will also investigate efficient test techniques for multi-level memristor based memories. The typical approach to testing a memory subsystem entails testing one memory cell at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by 27%.