2011 6th IEEE International Symposium on Industrial and Embedded Systems最新文献_第3页

Improving model-based verification of embedded systems by analyzing component dependences 通过分析组件依赖关系，改进嵌入式系统基于模型的验证

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953678

S. Siegl, Philipp Caliebe

{"title":"Improving model-based verification of embedded systems by analyzing component dependences","authors":"S. Siegl, Philipp Caliebe","doi":"10.1109/SIES.2011.5953678","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953678","url":null,"abstract":"Embedded systems in automobiles become increasingly complex as they are intended to make vehicles even more safe, comfortable, and efficient. International norms like ISO 26262 and IEC 61165 postulate methods for the development and verification of safety critical systems. These standards should ensure that the dependability and quality of the embedded systems is maintained while their complexity and interdependence increases. Yet, the standards do not contain concrete methods or tools for their fulfillment. As concerns classic techniques for dependability analysis they either base on system analysis by means of Markov analysis or on reliability estimation from a usage perspective. Treating the system only from one perspective, however, is a drawback as the system analysis neglects functional or non-functional dependences of the system. These dependences can directly influence the reliability in the field usage. In this paper we present our approach to combine component dependency models with usage models to overcome these deficiencies. It is possible to identify usage scenarios which aim for critical dependences and to analyze the interaction of components inside the system. On the other hand usage scenarios can be assessed whether they meet the desired verification purpose. The component dependency models reveal dependences that were not identified before, because it allows the extraction of implications across functional and non functional dependences like memory, timing and processor utilization.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130847011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Control-flow error detection using combining basic and program-level checking in commodity multi-core architectures 商品多核体系结构中结合基本和程序级检查的控制流错误检测

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953691

N. Khoshavi, H. Zarandi, M. Maghsoudloo

{"title":"Control-flow error detection using combining basic and program-level checking in commodity multi-core architectures","authors":"N. Khoshavi, H. Zarandi, M. Maghsoudloo","doi":"10.1109/SIES.2011.5953691","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953691","url":null,"abstract":"This paper presents a software-based technique to detect control-flow errors using basic level control-flow checking and inherent redundancy in commodity multi-core processors. The proposed detection technique is composed of two phases of basic and program-level control-flow checking. Basic-level control-flow error detection is achieved through inserting additional instructions into program at design time regarding to control-flow graph. Previous research shows that modern superscalar microprocessors already contain significant amounts of redundancy. Program-level control-flow checking can detect CFEs by leveraging existing microprocessors redundancy. Therefore, the cost of adding extra redundancy for fault tolerance is eliminated. In order to evaluate the proposed technique, three workloads quick sort, matrix multiplication and linked list utilized to run on a multi-core processor, and a total of 6000 transient faults have been injected on the processor. The advantage of the proposed technique in terms of performance and memory overheads and detection capability compared with conventional control-flow error detection techniques.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131023011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Video subset selection for measurement based Worst Case Execution Time analysis 基于最坏情况执行时间分析的测量视频子集选择

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953664

Sitsofe Wheeler, I. Bate, M. Bartlett

引用次数: 1

Extending Harmless architecture description language for embedded real-time systems validation 扩展嵌入式实时系统验证的无害体系结构描述语言

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953665

Jean-Luc Béchennec, M. Briday, Valere Alibert

{"title":"Extending Harmless architecture description language for embedded real-time systems validation","authors":"Jean-Luc Béchennec, M. Briday, Valere Alibert","doi":"10.1109/SIES.2011.5953665","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953665","url":null,"abstract":"Harmless is a hardware architecture description language targeted to the simulation of embedded and realtime software. It allows to describe the instruction set and the micro-architecture of a processor. From this description, the Harmless compiler generates an Instruction Set Simulator and a Cycle Accurate Simulator. Both simulators are useful to test and validate embedded software and the latter is essential for Real-Time software. Their use is cheaper and more comfortable than the execution on the actual hardware. Moreover, with simulation, it is easy and unobtrusive to trace the execution and to report useful informations. However, tracing mechanisms may be difficult or even impossible to integrate without ad-hoc support in the simulator and, in our case, in the description of the processor. This paper presents how Harmless is modified and used to add tracing support to simulators1. This mechanism called action is used to extract high level information such has the task scheduling observation and stack safety analysis from the low level simulation. It also highlights how the Harmless description of a processor should be updated to support these features and applies it on three processors models.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122856138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Model-based design of embedded control software for hybrid vehicles 基于模型的混合动力汽车嵌入式控制软件设计

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953684

Tizar Rizano, R. Passerone, D. Macii, L. Palopoli

引用次数: 5

Portability analysis of an M-JPEG decoder IP from OpenCores OpenCores M-JPEG解码器IP的可移植性分析

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953685

Xiaozhou Meng, Benny Thörnberg, N. Lawal

引用次数: 1

Implementing slot-based task-splitting multiprocessor scheduling 实现基于插槽的任务分割多处理器调度

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953669

Paulo G. Sousa, Björn Andersson, E. Tovar

{"title":"Implementing slot-based task-splitting multiprocessor scheduling","authors":"Paulo G. Sousa, Björn Andersson, E. Tovar","doi":"10.1109/SIES.2011.5953669","DOIUrl":"https://doi.org/10.1109/SIES.2011.5953669","url":null,"abstract":"Consider the problem of scheduling a set of sporadic tasks on a multiprocessor system to meet deadlines using a task-splitting scheduling algorithm. Task-splitting (also called semi-partitioning) scheduling algorithms assign most tasks to just one processor but a few tasks are assigned to two or more processors, and they are dispatched in a way that ensures that a task never executes on two or more processors simultaneously. A particular type of task-splitting algorithms, called slot-based task-splitting dispatching, is of particular interest because of its ability to schedule tasks with high processor utilizations. Unfortunately, no slot-based task-splitting algorithm has been implemented in a real operating system so far. In this paper we discuss and propose some modifications to the slot-based task-splitting algorithm driven by implementation concerns, and we report the first implementation of this family of algorithms in a real operating system running Linux kernel version 2.6.34. We have also conducted an extensive range of experiments on a 4-core multicore desktop PC running task-sets with utilizations of up to 88%. The results show that the behavior of our implementation is in line with the theoretical framework behind it.","PeriodicalId":391594,"journal":{"name":"2011 6th IEEE International Symposium on Industrial and Embedded Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131294740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

An exploratory case study of testing in an automotive electrical system release process 汽车电气系统释放过程测试的探索性案例研究

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953659

Daniel Sundmark, K. Petersen, S. Larsson

引用次数: 17

Robustness in real-time systems 实时系统的鲁棒性

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953652

N. Markey

引用次数: 37

Large drilling machine control code — Parallelisation and WCET speedup 大型钻床控制代码。并行化和WCET加速

2011 6th IEEE International Symposium on Industrial and Embedded Systems Pub Date : 2011-06-15 DOI: 10.1109/SIES.2011.5953688

M. Gerdes, Julian Wolf, Irakli Guliashvili, T. Ungerer, Michael Houston, G. Bernat, S. Schnitzler, Hans Regler

引用次数: 11